[Gems-users] disable Cache to cache connection in Gems

[Hamid Reza Khaleghzadeh <khaleghzadeh@xxxxxxxxx>]

Hi

I have simulated a quad-core processor by Gems that contains two L2
caches and each L2 is shared by two cores and coherency protocol is
MOESI-CMP-directory. I found that when a data misses in one of the L2
caches and this data exists in another L2, the data is read via L2
cache_to_L2 cache instead of memory. I intend to modify Gems where
when a miss occurs in L2, data is read from memory. Could you tell me
how i can do it?

Thanks for you answer in advance.