Re: [Gems-users] 回复： 回复： 回复： 回复： 回复： Latency and number of memory request

[Dan Gibson <degibson@xxxxxxxx>]

Memory controller internal delay models delay from logic pathways in the memory controller that don't fall into other categories. I.e., if you want to make the memory pipeline a little longer, add cycles there.

Regards,

Dan

2010/5/13 张轶 <zhangyi@xxxxxxxxxxxxxx>

Hi Dan,

Thanks for your help. My understanding is not correct.

 

Btw, in the MEM_CTL_LATENCY, does the "(four bit times) + (round trip on channel) " represent the time costed on data bus? And which delay does "memory controller internal delay" represent?

 

Regards,

Zhang Yi

 

 

------------------ 原始邮件 ------------------

发件人: "Dan Gibson"<degibson@xxxxxxxx>;

发送时间: 2010年5月12日(星期三) 晚上9:12

收件人: "Gems Users"<gems-users@xxxxxxxxxxx>;

主题: Re: [Gems-users]回复： 回复： 回复： 回复： Latency and number of memory request

 

Zhang,

According to my foggy recollection of the GEMS memory controller, MEM_CTL_LATENCY ends up as part of the enqueue-message delay, and BANK_BUSY_TIME is part of modeling the utilization of the banks themselves. E.g.:

At time T, a request is sent to Bank B. Total service time for that request is MEM_CTL_LATENCY + MEM_FIXED_DELAY, so when the request is issued, a response message is enqueued with that delay (the delay of the memory is modeled as a queueing delay in MemoryController.C). However, Bank B will be in operation servicing the request for BANK_BUSY_TIME, which is less than MEM_CTL_LATENCY, so the bank is marked as busy that number of cycles as well.

In other words, it is not double-charging for tRCT+CL+AL -- it is simply accounting for delay and contention.

Regards,

Dan

2010/5/12 张轶 <zhangyi@xxxxxxxxxxxxxx>

Hi Dan,

I am wondering if the default setting of request's latency in memory controller is wrong?

 

In the rubyconfig.default, there is the parameter "MEM_CTL_LATENCY: 12" with the comment "This equals tRCD + CL + AL + (four bit times) + (round trip on channel) + (memory control internal delays)".

And the BANK_BUSY_TIME is "Bank cycle time (tRC) measured in memory cycles".

 

In the memorycontroll.c, there is MemoryControl::issueRequest{

...

if (req.m_msgptr.ref() != NULL) {
    enqueueToDirectory(req, m_mem_ctl_latency + m_memFixedDelay);
  }

...

} and the m_mem_ctl_latency = MEM_CTL_LATENCY

 

So I think the MEM_CTL_LATENCY has been calculated in the memory request latency. Meanwhile in a request routine, the BANK_BUSY_TIME is also calculated in a memory request.

But in memory system, tRC includes tRCD + CL + AL .

 

According to those information, I am wondering if the latency of a request costed on memory controller has been calculated in additional time "tRCD + CL + AL "?

 

Regards,

Zhang Yi

 

 

--

http://www.cs.wisc.edu/~gibson [esc]:wq!

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