Re: [Gems-users] Regarding ruby miss rate

[Dan Gibson <degibson@xxxxxxxx>]

Out-of-order processors issue memory requests from false paths, and issue instruction fetch more aggressively, than in-order cores. Yes, the miss rates should be different, and should be noticeably different from short runs with cold caches.

Regards,

Dan

On Tue, May 11, 2010 at 10:25 AM, sparsh mittal ISU <sparsh@xxxxxxxxxxx> wrote:

Hello
Considering L2 miss rate to be (L2miss/L2access) or (L2miss/L1misses)
for both ruby+simics only and ruby+opal;
I am finding that the miss rates of L2 is different for ruby+simics
(doing c 100000) and ruby+opal (doing opal0.sim-step 100000).
May be it is a trivial question; but should the miss rates be
different. I would be grateful for some explanation.

--
Thanks and Regards
Sparsh Mittal
Graduate Student
Electrical and Computer Engineering
Iowa State University, Iowa, USA
_______________________________________________
Gems-users mailing list
Gems-users@xxxxxxxxxxx
https://lists.cs.wisc.edu/mailman/listinfo/gems-users
Use Google to search the GEMS Users mailing list by adding "site:https://lists.cs.wisc.edu/archive/gems-users/" to your search.

--
http://www.cs.wisc.edu/~gibson [esc]:wq!