[Gems-users] 回复： Latency and number of memory request

["张轶" <zhangyi@xxxxxxxxxxxxxx>]

Hi Dan,

Many thanks for your reply!  And I have two more questions.

 

1."There is a number that the target /thinks/ is the clock rate". Is this number the "basic cycle time of the memory controller"?  And which parameter defines this number?

Is this number different from the delay value used in the cache?

 

2. A stupid question. What is the "Demand accesses"?

 

Regards,

Zhang Yi

 

------------------ 原始邮件 ------------------

发件人: "Dan Gibson"<degibson@xxxxxxxx>;

发送时间: 2010年5月4日(星期二) 凌晨0:13

收件人: "Gems Users"<gems-users@xxxxxxxxxxx>;

主题: Re: [Gems-users] Latency and number of memory request

 

Hi Zhang,
Please see my answers below.

Regards,
Dan

2010/5/3 张轶 <zhangyi@xxxxxxxxxxxxxx>

Hi all!

I have two questions about memory request in gems.

1.The first is about the memory request latency in gems.

In the simics, the cycle value is decided by the processor frequency, in other words, this value is not a fixed value. It seems that gems cycle is multiple of simics cycle. Is it to say if the processor frequency in the simulation changes, then the latency value of a memory requestchanges too?

All latencies are measured in Ruby cycles. This cycle count is, in general, a multiple of a "Simics cycle". However, the definition of a "Simics cycle" is vague and difficult. This is why Ruby cycles is the measure of time -- strange things happen in 1 'simics cycle'. In theory, by having the SIMICS_RUBY_MULTIPLIER >1, GEMS 'emulates' a multi-issue in-order core. In practice, by modeling instruction fetch, this is not the case. However, I see you are using x86, so you may not be modeling instruction fetch anyway (see below).

Overall, there is no number measured in MHz that represents the processor frequency in GEMS. There is a number that the target /thinks/ is the clock rate, but it is by no means accurate.

2.On one processor, how many request a thread can issueat the same time?

In my simulation,I am using X86 arch and SMP protocal and simulate a 2 processor system. So there is no opal, thenwithout pipeline and without out of order instruction. To my understanding, for such a simulation,in each processor eachtime therewould issue two requests at the most(one is instruction cache miss the other is data cache miss)..

As of the time that I made my x86 patch, Simics's x86 model wouldn't actually do a stalling instruction fetch. This may have changed since I last looked/cared. You should find out, empirically if necessary or via the Simics Reference Manual.

That said, the Simics+Ruby model is even simpler than you assume. Instruction fetches and data accesses aren't issued concurrently.

So totally, inmy system there would have 4 requests waiting in the memory controller at the most. I have tried to print out all the memory requests in the simulation and found that at some time there would be at most6 requests waiting in the memory controller.So why?

My guess: Write-back caches + Demand accesses.

Many thanks!

Zhang Yi

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