> Hi Liu,
> I have seen this error in the past from opal under varying circumstances - it essentially means that simics was not ready for the read that opal is trying to perform. However, in spite of such exceptions, I have noticed that things to work alright for
the largest part. So, the simplest thing to do may be the Ostrich algorithm - try to run opal by ignoring the exception (like what Dan mentioned) and if all works fine, you don't have a problem :-).
>
> Cheers,
> Pradeep.
>
> On Mar 24, 2010, at 9:57 AM, Dan Gibson wrote:
>
>> This error is probably raised from opal/system/hfa.C, line 553.
>>
>> This is a generic routine to check whether a call into Simics completed without taking an error (unfortunately, this is called an exception, which is not the same as an exception in the target machine).
>>
>> In the case you observed, Opal is attempting to read from a physical memory address that Simics doesn't like. Bummer.
>>
>> I don't know why this might happen. I am not an opal expert in any fashion at all.
>>
>> One thing you might try is to ignore the exception. Here is some code that will do that. You could add it to hfa.C and see if opal crashes.
>> int isexcept = SIM_get_pending_exception();
>> while ( !(isexcept == SimExc_No_Exception || isexcept == SimExc_Break) ) {
>> SIM_clear_exception();
>> isexcept = SIM_get_pending_exception();
>> }
>>
>> Good luck.
>>
>> Regards,
>> Dan
>>
>> Hi guys,
>>
>> I build my ruby and opal under gcc-4.2 and it seems that the ruby module works fine. I builded opal with some efforts including copying some functions from cache.C to cache.h and modifying Makefile.
>> When I load opal module and init it, I meet some warnings. Then errors occurred when I tried to start the opal module as following.
>>
>> I have searched the user list to find that there is no solution to this question, although it occurred several times. I am a newbie to GEMS and any hints or help is heavily welcomed.
>> p.s. My machine is amd64-linux and the solaris10 operating system is booted under GEMS 2.1.1 (the newest version by now).
>>
>> Regards.
>> ================================================================
>> simics> instruction-fetch-mode instruction-fetch-trace
>> [cpu0 info] Note that on this cpu, instruction-fetch-trace is implemented using instruction-cache-access-trace with a suitable cache line size.
>> simics> istc-disable
>> Turning I-STC off and flushing old data
>> simics> dstc-disable
>> Turning D-STC off and flushing old data
>> simics> cpu-switch-time 1
>> The switch time will change to 1 cycles (for CPU-0) once all processors have synchronized.
>> simics> load-module ruby
>> successful installation of the ruby timing model.
>> simics> load-module opal
>> Queue registration cpu0
>> successful installation of the opal queue.
>> hfa_init_local done:
>> simics> ruby0.setparam g_NUM_PROCESSORS 1
>> simics> ruby0.setparam g_MEMORY_SIZE_BYTES 4294967296
>> simics> ruby0.init
>> Ruby Timing Mode
>> Creating event queue...
>> Creating event queue done
>> Creating system...
>> Processors: 1
>> Creating system done
>> Ruby: ruby-opal link established. removing timing_model.
>> OpalInterface: installation successful.
>> Ruby initialization complete
>> simics> opal0.init
>> pstate_t: warning: control register #0 == "(null)" has simics name "g0".
>> pstate_t: warning: control register #1 == "(null)" has simics name "g1".
>> pstate_t: warning: control register #2 == "(null)" has simics name "g2".
>> pstate_t: warning: control register #3 == "(null)" has simics name "g3".
>> pstate_t: warning: control register #4 == "(null)" has simics name "g4".
>> pstate_t: warning: control register #5 == "(null)" has simics name "g5".
>> pstate_t: warning: control register #6 == "(null)" has simics name "g6".
>> pstate_t: warning: control register #7 == "(null)" has simics name "g7".
>> pstate_t: warning: control register #8 == "(null)" has simics name "o0".
>> pstate_t: warning: control register #9 == "(null)" has simics name "o1".
>> pstate_t: warning: control register #10 == "(null)" has simics name "o2".
>> pstate_t: warning: control register #11 == "(null)" has simics name "o3".
>> pstate_t: warning: control register #12 == "(null)" has simics name "o4".
>> pstate_t: warning: control register #13 == "(null)" has simics name "o5".
>> pstate_t: warning: control register #14 == "(null)" has simics name "o6".
>> pstate_t: warning: control register #15 == "(null)" has simics name "o7".
>> pstate_t: warning: control register #16 == "(null)" has simics name "l0".
>> pstate_t: warning: control register #17 == "(null)" has simics name "l1".
>> pstate_t: warning: control register #18 == "(null)" has simics name "l2".
>> pstate_t: warning: control register #19 == "(null)" has simics name "l3".
>> pstate_t: warning: control register #20 == "(null)" has simics name "l4".
>> pstate_t: warning: control register #21 == "(null)" has simics name "l5".
>> pstate_t: warning: control register #22 == "(null)" has simics name "l6".
>> pstate_t: warning: control register #23 == "(null)" has simics name "l7".
>> pstate_t: warning: control register #24 == "(null)" has simics name "i0".
>> pstate_t: warning: control register #25 == "(null)" has simics name "i1".
>> pstate_t: warning: control register #26 == "(null)" has simics name "i2".
>> pstate_t: warning: control register #27 == "(null)" has simics name "i3".
>> pstate_t: warning: control register #28 == "(null)" has simics name "i4".
>> pstate_t: warning: control register #29 == "(null)" has simics name "i5".
>> pstate_t: warning: control register #30 == "(null)" has simics name "i6".
>> pstate_t: warning: control register #31 == "(null)" has simics name "i7".
>> pstate_t: warning: control register #99 == "(null)" has simics name "ecache_error_enable".
>> pstate_t: warning: control register #100 == "(null)" has simics name "asynchronous_fault_status".
>> pstate_t: warning: control register #101 == "(null)" has simics name "asynchronous_fault_address".
>> pstate_t: warning: control register #102 == "(null)" has simics name "out_intr_data0".
>> pstate_t: warning: control register #103 == "(null)" has simics name "out_intr_data1".
>> pstate_t: warning: control register #104 == "(null)" has simics name "out_intr_data2".
>> pstate_t: warning: control register #105 == "(null)" has simics name "out_intr_data3".
>> pstate_t: warning: control register #106 == "(null)" has simics name "out_intr_data4".
>> pstate_t: warning: control register #107 == "(null)" has simics name "out_intr_data5".
>> pstate_t: warning: control register #108 == "(null)" has simics name "out_intr_data6".
>> pstate_t: warning: control register #109 == "(null)" has simics name "out_intr_data7".
>> Ruby: ruby-opal link established. removing timing_model.
>> opalinterface: doing notify callback
>> Opal: opal-ruby link established.
>> OpalInterface: installation successful.
>> simics> opal0.sim-start "results.opal"
>> [0] PC 0xfffffffff0000020 NPC 0xfffffffff0000024 ctx 0x0
>> Exception error message: Physical memory read raised exception
>> FP registers: end
>> : caught exception (#7).
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