Re: [Gems-users] Counting CPU L2-Accesses

[Greg Byrd <gbyrd@xxxxxxxx>]

You can look at the source address of the cache request message to see which cache it came from.

...Greg


On 12/22/10 9:57 AM, Artur Podobas wrote:

Hi

Im currently running GEMS/RUBY under Simics simulating a system using the MSI_MOSI_CMP_directory. I have embedded some code to calculate the L1_Cache requests (misses and hits) from the local processor, but since the L2 Cache is shared amongst the entire chip, is there any possibility to record the L2 accesses (ie L1 misses) from a specific CPU to the shared L2 cache?

Best regards

Gray

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