Re: [Gems-users] L2 sharing in CMP

[Ikhwan Lee <ikhwan@xxxxxxxxxxxxxxx>]

As far as I know, L2 on a chip is always shared for all CMP protocols.
Plus, I would set g_NUM_L2_BANKS to be the same as g_PROCS_PER_CHIP (2
in your case) to have a reasonably banked last level cache (a NUCA
system).

The two components you are seeing are misses for each processor. It
seems like your processor 0 is showing a lot more misses than
processor 1. Are you running something on both processors?


On Fri, Apr 16, 2010 at 3:17 AM, sparsh mittal ISU <sparsh@xxxxxxxxxxx> wrote:
> I found the following command in Profiler.C
>
>  m_perProcTotalMisses.setSize(RubyConfig::numberOfProcessors());
>
> This sets the vector  m_perProcTotalMisses to have size=2.
>
> So, how should I set the parameter that L2 can be shared?
> Thanks
> Sparsh
>
> On Thu, Apr 15, 2010 at 1:01 PM, sparsh mittal ISU <sparsh@xxxxxxxxxxx>
> wrote:
>>
>> Hello All
>> I am trying to simulate with MOESI_CMP_directory protocol.
>> I gave the following command
>>
>> load-module ruby
>> ruby0.setparam g_NUM_CHIPS 1
>> ruby0.setparam g_NUM_PROCESSORS 2
>> ruby0.setparam g_PROCS_PER_CHIP 2
>> ruby0.setparam g_NUM_L2_BANKS 1
>> ruby0.init
>>
>> To ensure that there is one L2 shared on the chip. However, when I see the
>> stats file, I find:
>> Total_misses: 25857
>> total_misses: 25857 [ 25209 648 ]
>>
>> I was thinking that if there is just one L2, then why should the total
>> misses in L2 be composed of two components?
>> Any suggestion is appreciated.
>> --
>> Thanks and Regards
>> Sparsh Mittal
>> Graduate Student
>> Electrical and Computer Engineering
>> Iowa State University, Iowa, USA
>
>
>
> --
> Thanks and Regards
> Sparsh Mittal
> Graduate Student
> Electrical and Computer Engineering
> Iowa State University, Iowa, USA
>
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