Hi,
I am using hierarchical switch topology and MOSI_SMP_bcastprotocol.
In one processor case, I got the following network stats. (I deleted
the utilization part)
switch_0_inlinks: 1
switch_0_outlinks: 1
outgoing_messages_switch_0_link_0_Control: 15049 120392 [ 15049 0 0 0
] base_latency: 1
switch_1_inlinks: 1
switch_1_outlinks: 1
outgoing_messages_switch_1_link_0_Data: 15049 1083528 [ 0 15049 0 0 ]
base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
outgoing_messages_switch_2_link_0_Control: 15049 120392 [ 15049 0 0 0
] base_latency: 1
outgoing_messages_switch_2_link_0_Data: 15049 1083528 [ 0 15049 0 0 ]
base_latency: 1
outgoing_messages_switch_2_link_1_Control: 15049 120392 [ 15049 0 0 0
] base_latency: 1
>From previous posts, someone said that 1 switch is for processor, 1
switch is for L2 bank and others are internal switches. But isn't
processor only connected to L1 caches? From the figure of ruby on gems
wiki, L1, L2 and directory/memory are connected to the network. In the
one processor case, how to interpret the switches?
Here, I think switch 2 should be the internal one. But how can switch 2
has 2 links containing control messages?
In the multi-processor case, there is one L2 cache for each chip. Are
those L2 caches shared or private? I haven't seen any specification of
this.
Thank you for the help!
Best
-Zhen
--
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Zhen WANG
Ph.D. Student
Department of Electrical and Computer Engineering
Rice University, Houston, Texas
http://www.owlnet.rice.edu/~zw3/
http://www.recg.org/
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