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Hi Dan,
I have tried to transfer memory channel bits to the highest bits in the address mapping, and also tried to set the channel bits above the rank bits. There both comes out the same error:
Fatal Error: in fn virtual void Sequencer::wakeup() in system/Sequencer.C:161: Aborting
Abort (SIGABRT) in main thread
The simulation state has been corrupted. Simulation cannot continue.
Please restart Simics.
Warning: in fn virtual void Sequencer::wakeup() in system/Sequencer.C:153: request is [CacheMsg: Address=[0x723f3c, line 0x723f00] PhysicalAddress=[0x723f3c, line 0x723f00] Type=ST ProgramCounter=[0xc0440537, line 0xc0440500] AccessMode=SupervisorMode Size=4 Prefetch=No Version=0 LogicalAddress=[0xc0723f3c, line 0xc0723f00] ThreadID=0 Timestamp=0 ExposedAction=0 Time=2494 ]
.
.
.
Then I tried to comment out "if (current_time - request.getTime() >= g_DEADLOCK_THRESHOLD)" in Sequencer::wakeup(), then there comes out
simics> c ruby0.init
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
Processors: 2
id: 1804289383
id: 846930886
Creating system done
Ruby initialization complete
simics> c
*** Event queue overflowed (limit reached) - stopped.
Increase sim.event_queue_max (currently 4096) if this is
not an error symptom.
I would like to ask is it possible to transfer the controller bits to other place in the address mapping? How should I do?
Many thanks!
Zhang Yi
------------------ 原始邮件 ------------------
发送时间: 2010年4月9日(星期五) 中午1:12
收件人: "Gems Users"<gems-users@xxxxxxxxxxx>;
主题: Re: [Gems-users] How to config memory system
>From what you've shown me, there's a bug in the profiling. It would seem there is only one set of /profiled statistics/ for memory controllers in the system. There actually are (or appear to be) several physical controllers, for what thats worth. My earlier suggestion (the reduction-AND and reduction-OR) could still prove or disprove whether or not there are multiple instantiated controllers (properly multiplexed on one address bit). Regards, Dan
2010/4/8 张轶 <zhangyi@xxxxxxxxxxxxxx>
Hi Dan,
It seems the profiler in GEMS can't distinguish different memory controllers. In source code, there is:
//for memory control
void Profiler::profileMemReq(int bank) {
m_memReq ++;
m_memBankCount[bank] ++;
}
And in the run time, I haven't found multiple profiler instantiations in system.
If so, and there are two memory controllers, the profiler will add up two statistics for the bank [i] as one single profiled result. Thus it appears to me there is only one set of memory controller in the system.
Please correct me if i am wrong.
Best regards,
Zhang Yi
------------------ Original ------------------
Date: Fri, Apr 9, 2010 00:18 AM
Subject: Re: [Gems-users] How to config memory system
Zhang, If BANKS_PER_RANK = k, then all memory controllers should be able to access banks [0,k). This because with two memory controllers, there are 2*k total banks (assuming only one rank in this example). If you keep the reduction-OR and reduction-AND of all addresses observed at each memory controller, you should find one MC always has one bit SET, and the other controller always has the same bit CLEARED (for the special case of Num_MCs = 2). Regards, Dan
2010/4/8 张轶 <zhangyi@xxxxxxxxxxxxxxx>
Hi Dan,
I refer to banks of memory.
In the input port of each memory controller, I print out the bank Id of each access. And the results show that each memory controller serves all memory banks. What's your opinion?
Best regards,
Zhang Yi
------------------ Original ------------------
Date: Thu, Apr 8, 2010 09:19 PM
Subject: Re: [Gems-users] How to config memory system
Zhang,
What exactly did you print? Requests should already be multiplexed between memory controllers based on address, but it should be possible for each memory controller to access of of its own banks. The term 'bank' appears a lot in GEMS - the L2 has banks, the memory controller has banks -- to which banks do you refer?
Regards,
Dan
Hi Dan,
I have performed such a experiment: print out all the banks a memory controlleraccessed,in MOSI_SMP_bcast_m protocol, with 2 processors.
The result shows that all the banks can be accessed by both memory controllers.
In the real DRAM system, the banks accessedby one channel cannot be accessed by another channel and accesses between different channels won't be stalled. Since in GEMS, memory controller = channel, then if, at thesame time,each memory controller/channel canaccess all the banks, what is themechanism of thememory controller in GEMS? Is itright to sayin GEMS,there happens that multiple accesses from different channels contend forone bank?
Best Regards,
Zhang Yi
------------------Original------------------
Date: Wed, Apr 7, 2010 10:03 PM
Subject: Re: [Gems-users] How to config memory system
I believe the bits that determine which controller to use are hard-coded into Ruby.Look at the function map_Address_to_DirectoryNode in RubySlicc_ComponentMapping.h. Regards, Dan
2010/4/7 张轶 <zhangyi@xxxxxxxxxxxxxx>
Hi Dan,
I have read rubyconfig.defaults carefully and do some experiments. It seems that the address mapping that determines which bits to denote the channel dosen't appear in the rubyconfig.defaults.
You mean the address mappings for channel bits should be configured in topology files, right? Would you tell me which files I should refer to?
Thanks,
Zhang Yi
------------------ Original ------------------
Date: Tue, Apr 6, 2010 10:04 PM
Subject: Re: [Gems-users] How to config memory system
1. In rubyconfig.defaults, there are 17 configuration variables affecting the MemoryController. Read the comments. 2. The number of memory controllers will depend on your topology. Regards, Dan
2010/4/6 张轶 <zhangyi@xxxxxxxxxxxxxxxxx>
Hi Dan,
Thanks for your help. But unfortunately, I am still not clear how to configure the memory controller.
1)In the rubyconfig.defaults, there is no configurations for the memory controller/channel. So how to assign which address bits to denote channels?
2)My system is configured with MOSI_SMP_bcast_m protocol, 2 processors...... The other settings are followed by rubyconfig.defaults. BANKS_PER_RANK: 8, RANKS_PER_DIMM: 2, DIMMS_PER_CHANNEL: 2 ....
In the memorycontrol instantiation, I have added an random function, and through the data printed out, I suppose there should be two memory controllers/channels, thus there would be totally 64 banks, doubles of 32.
But through typing command dump-stats, I could only read 32 banks, namely half statistics.
So, why?
Any advice will be appreciated!
Zhang Yi
------------------ Original ------------------
Date: Sat, Apr 3, 2010 10:43 PM
Subject: Re: [Gems-users] How to config memory system
1. The number of memory controllers is a function of the network topology. They appear in the topology as "Directory Memory" objects. This is true regardless of whether you happen to be using a 'CMP' or 'SMP' protocol. 2. Memory controllers are shared by all processors. 3. In GEMS, Memory Controller = Memory Channel. Bonus extra response: Only protocols that end in _m actually use a realistic memory controller. All other protocols just assume memory has a fixed latency. Regards, Dan
Hi, all
Currently, I am using GEMS 2.1 to perform simulation andhavesome confusions on memory configs:
1. I am wondering, inGEMShow to set the numbers ofmemory controllerfor CMP and SMP system? Isit the same in both CMP and SMP?
2. Will memory controller be shared by all processors?
3.Is memory controller the same thingto memory channels?
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