Re: [Gems-users] Finding the values of latency

[Rakesh Komuravelli <komurav1@xxxxxxxxxxxx>]

I have a small question on the same topic.

I think L1 hit latency is SEQUENCER_TO_CONTROLLER_LATENCY only when REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH is set to true. Else, the default latency for L1 hit is 0 cycles (whole transaction thus takes 1 cycle as Simics executes one instruction per cycle). Please correct me if I am wrong.

I am using MESI_SCMP_bankdirectory protocol. Does it make sense to set REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH to false for CMP protocols? https://lists.cs.wisc.edu/archive/gems-users/2006-August/msg00097.shtml talks about this but the discussion doesn't say that CMP protocols must set the flag to true.

Thanks,

Rakesh

On Sat, Nov 28, 2009 at 5:06 PM, Philip Garcia <pcgarcia@xxxxxxxx> wrote:

On Nov 28, 2009, at 4:46 PM, sparsh mittal ISU wrote:

> Hello
> Thanks a lot list-users for the previous replies.
> While using the default configurations (no change) for ruby and opal
> in gems-2.1 what is the value of L1, L2 and memory latency that is
> used? I tried to see the config files, but could not understand the
> right value, amongst the variety of values of latencies.
> I would appreciate any help.
>

It really depends on what protocol you use for what the latencies you
get.  I use MOESI_CMP_directory_m for my research.  In other protocols
the latencies are often completely different.  I had a conversation
with Derek recently about the latencies involved in different
scenarios, and I am pretty sure this is what we came up with (please,
correct me if I'm wrong).


L1 hit:  Sequencer to Controller latency

L1 Miss, L2 hit:        1.  seq 2 controller
                               2.  L1 Req latency
                               3.  Network
                               4.  L2 response latency
                               5.  Network

L1 Miss/L2 Miss/other L1 hit:
1.  seq 2 controller
                               2.  L1 Req latency
                               3.  Network
                               4.  L2 response latency
                               5.  Network
                               6.  L1 Req latency
                               7.  Network
                               8.  L1 req latency
                               9.  Network

I think on an L2 miss ->main memory it goes

L1 Miss, L2 hit:        1.  seq 2 controller
                               2.  L1 Req latency
                               3.  Network
                               4.  L2 response latency
                               5.  Network
                               6.  directory latency
                               7.  memory latency (set by a whole bunch of parameters in the _m
protocols, check the default files for details).
       --not sure if there is other on chip latencies here i'm skipping
though, as we didn't discuss this case much.

Phil

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