[Gems-users] CMP of SMTs in Ruby/Simics

[Konstantinos Botsaris <kbotsaris@xxxxxxxxxxxxxxxxx>]

Hello list,
i am trying to simulate a CMP of SMTs in ruby/simics using an SMP 
protocol with chips acting like smt cores and processors like threads. I 
am thinking of using MOESI_SMP_directory protocol which provides a 
common L2 cache for all the chips exactly as i want. The problem is that 
each ruby processor has its private L1 cache which i have to unify with 
all the others in the same chip so that the processors on the same chip 
act like threads and the chips like processors(cores). to begin with i 
am thinking of issuing makeRequests in SimicsDriver.C from processors of 
the same chip only to one of them. The stats for that ruby 
processor(thread) will be the stats of its SMT core(chip). Any 
suggestions or any other ideas??? Thanks!
Konstantinos