[Gems-users] A question to the MSI_MOSI_CMP_directory protool

[Peng Deng <dengpeng@xxxxxxxxx>]

Hello,

I've been trying to understand how the L1/L2 cache states change
according to MSI_MOSI_CMP_directory protocol provided by Ruby. I would
like to know with this protocol and in the situation that one
processor (PROC1) changes a cache line shared by another processor
(PROC2) and then PROC2 reads the same cache line, if the L2 cache will
issue a forced downgrade to PROC1's L1 cache and provides the updated
data to PROC2 (so that an access to physical memory can be avoid)?

Regards,
P.D.