Date: | Thu, 19 Mar 2009 11:52:39 -0400 |
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From: | Edward Lee <edwl202@xxxxxxxxx> |
Subject: | Re: [Gems-users] Coherence misses |
Thanks Dan for your reply. I assume you are referring to "Chip Stats" section. I thought about that I was a little confused. I am using MOSI_SMP_bcast, which means there is only one SLICC controller for L1 and L2 caches. Is this the reason I only see "L1Cache" under Chip Stats? Here is my output showing L1Cache and directory events. I think these are the totals for various other transition options from various cache states but anyways totals are fine for my purpose. I just want to verify my understanding here as I am not very confident with my interpretation: I am not sure how to understand whether I used inclusive caches or not but I believe L2 cache is inclusive and since only one controller is present, cache-to-cache transfers only occur between different L2s. And below stats show actually those L2 stats and for coherence misses I should look at "L1Cache" stats not directory stats. And finally I am thinking of coherence misses as --> (Total of Other_* ) and the percentage of coherence misses as -->(Total of Other_* ) / (Total of all event counts in cache stats) --- L1Cache --- - Event Counts - Load 133041 Ifetch 0 Store 56336 L1_to_L2 176418 L2_to_L1D 101743 L2_to_L1I 0 L2_Replacement 9650 Own_GETS 82664 Own_GET_INSTR 0 Own_GETX 44650 Own_PUTX 5091 Other_GETS 578648 Other_GET_INSTR 0 Other_GETX 312550 Other_PUTX 0 Data 118632 ..... --- Directory --- - Event Counts - OtherAddress 0 GETS 82664 GET_INSTR 0 GETX 44650 PUTX_Owner 5091 PUTX_NotOwner 0 Regards, Ed On Thu, Mar 19, 2009 at 9:04 AM, Dan Gibson <degibson@xxxxxxxx> wrote: Total_misses are L2 misses -- probably not what you want. Towards the bottom of the stats file, there should be a summary of protocol transitions. Depending on your protocol, you should be able to get a notion of how many 'coherence misses' there are. |
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