[Gems-users] Failed assertion in CacheMemory<ENTRY>::deallocation

[Peng Deng <dengpeng@xxxxxxxxx>]

Hello All,

I've been experimenting with GEMS for a software controlled L1 data
cache flushing approach. I learned from some threads in this mailing
list and modified RubySlicc_exports.sm by adding a new
CacheRequestType, and also convert the request to event
"L1_Replacement" in MSI_MOSI_CMP_directory-L1cache.sm
(mandatory_request_type_to_event). I then added new functions in
Sequencer.C as following

    void Sequencer::flushL1Cache(int cpu, const Address& addr, int
requestSize) {
        Time latency = SEQUENCER_TO_CONTROLLER_LATENCY;
        CacheMsg msg;
        msg.setAddress (addr);
        msg.setType(CacheRequestType_INVALIDATE);
        msg.setSize(requestSize);
        cout << "Flushing L1 Data cache at ";
        addr.print(std::cout);
        cout << endl;
        m_chip_ptr->m_L1Cache_mandatoryQueue_vec[m_version]->enqueue(msg,
latency);
        cout << "Done flushing." << endl;
    }

I also changed the "magic_instruction_callback" in
ruby/simics/commands.C so I can trigger the flushing function in
sequencer by using simics's magic instruction.

    ...
    } else if (val==10000) {
        Sequencer *targetSequencer_ptr =
g_system_ptr->getChip(proc_num/RubyConfig::numberOfProcsPerChip())->getSequencer(proc_num%RubyConfig::numberOfProcsPerChip());
        pa_t physicalAddr = SIM_logical_to_physical((conf_object_t*)cpu,
                                                      Sim_DI_Data,

SIMICS_read_register(proc_num, SIMICS_get_register_number(proc_num,
"g1")));

        int requestSize  = SIMICS_read_register(proc_num,
SIMICS_get_register_number(proc_num, "g2"));
        Address addr;
        addr.setAddress(physicalAddr);
        addr.makeLineAddress();
        targetSequencer_ptr->flushL1Cache(proc_num, addr, requestSize);

I wrote a simple program to test this out, but I got the following
error in simics console:

    Flushing L1 Data cache at [0x375b3d80, line 0x375b3d80]
    Done flushing.

    failed assertion 'isTagPresent(address)' at fn void
CacheMemory<ENTRY>::deallocate(const Address&) [with ENTRY =
L1Cache_Entry] in system/CacheMemory.h:453
    failed assertion 'isTagPresent(address)' at fn void
CacheMemory<ENTRY>::deallocate(const Address&) [with ENTRY =
L1Cache_Entry] in system/CacheMemory.h:453
    At this point you might want to attach a debug to the running and get to the
    crash site; otherwise press enter to continue
    PID: 31392

It seems the address I wanted to flush doesn't exist in L1D cache? Is
there anything that I did wrong? Could anyone please give some hints
on how to debug this? I'm pretty new to Simics+GEMS. Thanks a lot.

Cheers,
Peng