Re: [Gems-users] MSI_MOSI vs MOESI directory protocols (Miss Rate & IPC)

[Dan Gibson <degibson@xxxxxxxx>]

Cost of all misses ~= number of accesses * miss rate * cost of individual miss.

To first order, number of accesses between two protocols is roughly the same.
As you observe, miss rate is a function of protocol, however, so is the cost of individual misses. I do not know the details of either of those protocols, but there is a wide variety in how messages are ferried about the chip, what messages are needed, etc., that affect the average cost of an individual miss. After all, that is one of the compelling reasons to do research on coherence protocols.

Regards,
Dan

On Thu, Jul 9, 2009 at 9:23 PM, David Bonavila <david.bonavila@xxxxxxxxxxxxxxxxxx> wrote:

Hi,

I am comparing these 2 protocols, and I found something that doesn't make much sense.
MOESI has a higher miss rate (about 5%) than MSI_MOSI, but also has a higher IPC (about 0,06).
As I understand, the higher miss rate we have, the lower IPC we get, isn't that right?? 

The simics scripts are the same and they are run twice, once with each of the protocols.
Same workloads also (several PARSEC benchmarks).

Comparing the Ruby configuration files, all parameters seem to be the same, also latencies.
The only difference I can see is that MSI_MOSI has 5 virtual networks and MOESI has only 3 virtual networks.
Can this be the reason of that higher IPC??

Or maybe what makes such difference is that MSI_MOSI is inclusive and MOESI is not??

The descriptions for these protocols say:
    * MSI_MOSI_CMP_directory: A two-level directory protocol for Chip-Multiprocessors.
                            The L1 and L2 controllers are split, and the L2 cache is shared by all processors on the same chip.
                            Inclusion is maintained between L2s and the L1s, and a sharers list is kept in each L2 cache line.
    * MOESI_CMP_directory: A two-level directory protocol for Chip-Multiprocessors.
                            Non-inclusive L1/L2 caching with blocking caches.


I guess the results are correct, but can anyone tell me WHY IPC is higher even thought miss rate is also higher??

Thanks!!


Regards,
David

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