Re: [Gems-users] L1 cache to processor Latency

[Javier Merino <jmerino@xxxxxxxxxxxxx>]

El lun, 23-02-2009 a las 14:28 +0100, Marco Solinas escribió:
> Hi list,
> 
> I was wandering if it is possible to specify a L1cache to processor 
> latency in case of hit. When a request message is peeked from the 
> MandatoryQueue, and the requested block hits in L1cache, the transition 
> invokes the callback action, that invokes the corresponding callback 
> function of the sequencer. Is it possible to specify a "custom" response 
> latency in such cases? In case it is possible, how can I do that? 
> Otherwise, how many cycles this latency is assumed to be (and 
> eventually, where it is specified)?

When a processor makes a request, it waits
"SEQUENCER_TO_CONTROLLER_LATENCY" cycles before appearing in the
MandatoryQueue (see Sequencer::issueRequest in ruby/system/Sequencer.C).
You can control the L1 hit time with that parameter (4 by default). Take
into account that misses also wait that amount of time before you see
them in the MandatoryQueue, so you may need to adjust your miss time
accordingly.

Hope this helps, regards,
Javi

> Thanks in advance for your support.
> Regards
> Marco
> 
> 
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