Re: [Gems-users] Does gems (ruby) model the DMA operations now?

[Sitos Lin <sitos.lin@xxxxxxxxx>]

Hi:
  Thank you for your reply. Maybe I can simplify my question. If there
is a loop, in which a DMA operation fetches data from files to a
predefined array with fixed size, does this loop incur a lot of cache
misses every iteration? If the effect of DMAs is models, the loop
should incur cache misses every iteration, because the data are not
cached in the cache. However, if the effect of DMAs is not models,
since the data of array (of their address) are in the cache, the
memory accesses to these addresses may result in cache hits instead of
cache misses. So, what situation would happen?
Best regards,
  Sitos

2009/12/18 Muhammad abid Mughal <mabidm_pieas@xxxxxxxxx>:
> hi
> I do know that Ruby does not support DMA requests even in gems-2.1. It just
> filters them out via SimicsDriver::isunhandledtransaction(), so its not
> possible for DMA requests to invalidate the corresponding cache blocks in
> L1/L2 caches[i am wondering that DMA accesses I/O blocks and Ultrasparc
> processor does not allow caching of i/o blocks, so no question of
> invalidating corresponding L1$/L2$ blocks.am i right?]
> Regards,
> Muhammad abid
> ________________________________
> From: Sitos Lin <sitos.lin@xxxxxxxxx>
> To: gems-users@xxxxxxxxxxx
> Sent: Friday, December 18, 2009 11:24:41
> Subject: [Gems-users] Does gems (ruby) model the DMA operations now?
>
> Hello all:
>   I want to use gems (ruby) to capture the memory access trace.
> However, I am wondering if gems models the DMA operations. In the
> paper, it says "Also, Ruby does not model the memory system traffic
> due to direct memory access (DMA) operations or memory-mapped I/O
> loads and stores." However, gems is now version 2.1. Does gems model
> the DMA operations now?
>   Besides that, if the memory system traffic of DMA operations are not
> modeled, I want to know if DMA operations invalidate the correspondent
> cache blocks in L1/L2 caches. Since the values of memory have been
> changed by DMA (read) operations, the cache blocks should be
> invalidated and the following cache accesses to these lines should be
> miss. I have tried to test gems by two simple program. However, the
> results are not consistent to my knowledge. The program with
> additional DMAs causes less cache misses than another one without DMA
> operation.
>   If gems can not model the features mentioned above, I will try other
> approaches.
> Best regards,
>   Sitos
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