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Hi Jungwook,
GEMS is a detailed memory system simulator. So, it does check L1, then L2 and only then memory. However, the important bit is that as GEMS is right now, it is only a detailed timing simulator, so the cache protocol does not keep track of the data. You will get the most recent data, but not by virtue of the coherence protocol, but via simics.
Hope this helps.
Polina
On Fri, Nov 27, 2009 at 6:46 AM, 조정욱 <jmanbal@xxxxxxxxx> wrote:
Dear Gems User,
Hello, I'm conducting a research project on NUCA architecture.
So I used simics and tried to modify simics code.
The simics version I used is 3.0.
Today, I know that the cache simulation the Simics support didn't save data.
I mean g-cache save just tag and main memory address.
Is it right??
I heard the Gems is able to simulate cache( absolutely NUCA ).
I wander the cache to support Gems save the data???
For exampler,
When cpu wants data, first check L1 cache and then L2 cache and finally main memory.
If the data exist in L1 cache, cpu receive the data from L1 cache.
plz explain in detail.
Thank you for consideration.
Best regards,
Jungwook
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