Re: [Gems-users] setting L2 cache latency in MOESI_CMP_directory_m

[Niket Agarwal <niketa@xxxxxxxxxxxxx>]

Hi Phil,

What network are you using? And how many nodes are there in your system? 
The actual network delay can be much higher than the specified link 
latencies.
Also, you might want to ensure that the RANDOMIZATION flag is set to 
false. Otherwise messages get added "random" delays when enqueued into 
the MessageBuffer. If you are running with Simics, the default is false.
-Niket

Philip Garcia wrote:
> Hello,
> I am trying to tweak my L2 cache miss latencies, however it seems that  
> whatever I do, I end up having a latency of over 40 cycles to my L2,  
> which is very unrealistic.  I have set the standard latencys to be  
> relatively reasonable (and even tried ridiculously low values.  Here  
> is a small trace of execution showing an issue to a memory address,  
> and the wakeup times (when enabling SLICC_DEBUG) that I see.  I've  
> added a bit more to the outputs to show cycle times, and the latency  
> being added (for instance, the GETS request shows the latency it adds  
> before putting the requests on the request queue.
> 108079: L1 issuing GETS on chip 1 for addr [0xd388680, line 0xd388680]  
> new latency adding 2
> 108079: L1 issuing GETS on chip 1 for addr [0xd3886c0, line 0xd3886c0]  
> new latency adding 2
> 108081: ../protocols/MOESI_CMP_directory-L1cache.sm:331: MRM_DEBUG: L1  
> received
> 108081: ../protocols/MOESI_CMP_directory-L1cache.sm:332: WB_ACK_DATA
> 108081: ../protocols/MOESI_CMP_directory-L1cache.sm:331: MRM_DEBUG: L1  
> received
> 108081: ../protocols/MOESI_CMP_directory-L1cache.sm:332: WB_ACK_DATA
> 108099: ../protocols/MOESI_CMP_directory-L2cache.sm:885: [0xd388680,  
> line 0xd388680]
> 108100: ../protocols/MOESI_CMP_directory-L2cache.sm:885: [0xd3886c0,  
> line 0xd3886c0]
> 108120: ../protocols/MOESI_CMP_directory-L1cache.sm:654: MRM_DEBUG: L1  
> decrementNumberOfMessages
> We recieved something for chip 1 on node 0 Addr:[0xd3886a0, line  
> 0xd388680] Extra node handler working.  It Took 43 cycles!
> 108122: ../protocols/MOESI_CMP_directory-L1cache.sm:654: MRM_DEBUG: L1  
> decrementNumberOfMessages
> We recieved something for chip 1 on node 0 Addr:[0xd3886c0, line  
> 0xd3886c0] Extra node handler working.  It Took 45 cycles!
> After running this, it appears that the L2 cache doesn't receive my  
> data for 20 cycles, and doesn't return the data back for another 20  
> cycles.  I'm not sure which latency I'm missing here, but I thought an  
> L2 cache hit was just SEQUENCER_TO_CONTROLLER_LATENCY 
> +L1_REQUEST_LATENCY+L2_RESPONSE_LATENCY.  I know there's also a little  
> added for network link latencies, but for now, I've set all of those  
> to 1.
> If anyone knows something that I'm missing, I'd greatly appreciate  
> their help.
> Phil
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