Re: [Gems-users] L1 Cache Invalidation

["Ashwath Narasimhan" <nashwath@xxxxxxxxx>]

1. Can I do this by looking at the Access Permission by using the function GetPermission in cacheMemory.h. If AccessPermission is Invalid then I know that the cache line for that particular processor is invalid. Am I right?

On Fri, Nov 28, 2008 at 6:19 PM, Xuehai Qian <xuehaiq@xxxxxxxxx> wrote:

You should look at the protocol described in ruby, you can notify the current processor the change of cache line state by a remote processor.

 

Xuehai

On Fri, Nov 28, 2008 at 4:56 PM, Ashwath Narasimhan <nashwath@xxxxxxxxx> wrote:

Hi,
How can i know if the L1 cache block for a particular processor is invalid due to modification of a word in the same block by another processor?

Where in code should I look at to tap this ?


regards,
ashwath

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