Re: [Gems-users] Couple of questions

["Mike Marty" <mike.marty@xxxxxxxxx>]

On Wed, Nov 12, 2008 at 7:23 PM, Arkaprava Basu <basu@xxxxxxxxxxx> wrote:

Hi All,

           For my project I need to know about couple of following things,

1> I need to know about how can we modify the access latency and
bandwidth of the main memory. Any leads on what are the function calls
to the memory controllers, will be helpful too. I also need to have two
different latency and b/w for two different portions of the physical
memory. Any idea on how to achieve this?

see the -dir.sm files in $GEMS/slicc for where the naive memory access is performed. 

The memory latency is controller by a parameter in $GEMS/config/rubyconfig.defaults

The bandwidth can be constrained by setting the bandwidth of the appropriate link that connects the DirectoryMemory controller (specified in the -dir.sm file)

I believe there has been work done on a more realistic memory controller implementation since I left the university.  Thus the bandwidth might be more directly controlled.   

2> I need to invalidate few specific cache blocks in the cache hierarchy
( in both L1 and L2) in case of a particular event in the system. Any
idea on how can I accomplish this?

You will need to add an invalidate type to CacheRequest.  These are initialized in the per-processor Ruby sequencer.  

--Mike