Re: [Gems-users] which protocol can I use?

[Huan Fang <huanf@xxxxxx>]

For SCMP protocol, is it possible to distribute memory among all cores. 
I mean the num_of_memories is the same as num_of_processors. or can I 
realize interleaved memory based on this protocol? Thank you.
Huan
> >  Thanks for your explanations.  I have noticed there is a
> >  MESI_SCMP_bankdirectory protocol. If the directory in L2 only maintains
> >  L1 tags  then I think it's not what we need. There is no off-chip
> >  coherence requirement for SCMP so there is no need for a directory in
> >  memory, am I right?
> >
> >     
> Excellent point.
>
>   
> >  As for our system, I think it's more like the SMP protocol in GEMS,
> >  though it's a cc-NUMA architecture. Is there any changes we should make
> >  if we use MOESI_SMP_directory protocol?  When you said "L2 caches must
> >  be private and exclusive with the L1s", I don't fully understand why it
> >  must be exclusive?
> >
> >     
> The SMP L1/L2s must be exclusive to relieve the cache controller of
> managing the tag for a block in more than one cache.
>
> The SMP protocols will, be default, assume the number of
> directory/memory controllers is equal to the number of processors.
> You can hack around this by modifying RubyConfig.C (I think).
>
> --Mike
>
>
>
>   
> >  Regards,
> >  Huan
> >
> >     
> > > By default, the *CMP* protocols treat the caches on a single "chip" as
> > >       
> >  > shared.  You can change this behavior by changing the
> >  > map_L1Cache_to_L2Cache (or something like that) in
> >  > ruby/slicc_interface/ruby_slicc_component_mapping.h.  In fact there
> >  > might even be a function called map_L1Cache_to_PrivateL2Cache still in
> >  > there.  If not, consider adding it.
> >  >
> >  > The *SMP* protocols use a single cache controller to model both L1 and
> >  > L2 caches.  Hence L2 caches must be private and exclusive with the L1s.
> >  >
> >  > The *CMP* protocols have more complexity because they support
> >  > Multiple-CMP systems.
> >  >
> >  > I believe there is an SCMP protocol that is for single-chip use.  It
> >  > has separate L1 and L2 cache controllers.  You would have to change
> >  > the mapping function to make the L2 private.
> >  >
> >  > --Mike
> >  >
> >  >
> >  > On Mon, Mar 24, 2008 at 7:30 AM, Huan Fang <huanf@xxxxxx
> >
> >     
> > > <mailto:huanf@xxxxxx>> wrote:
> > >       
> >  >
> >  >     Hi everyone,
> >  >
> >  >     It's my first post here :) I need some help to decide which protocol
> >  >     best suits my project.
> >  >     Since we are considering a CMP architecture with 16 processors on one
> >  >     chip, but each processor has its private L1,L2, even memory,(the
> >  >     memory
> >  >     is shared but physically distributed), shall I use
> >  >     MSI_MOSI_CMP_directory or MOESI_CMP_directory? However, they have two
> >  >     level directories, do we need the L1-L2 cache coherence protocol?
> >  >     Maybe we can use MOESI_SMP_directory, because it's said "The SMP
> >  >     protocols can be used to model a CMP with Private caches."
> >  >     Any reply are welcome. Thank you.
> >  >
> >  >     Regards,
> >  >     Huan
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