[Gems-users] Shared memory access on multicores

["Cihat Basol" <cihatbas@xxxxxxxxxxxxxxx>]

Hi,

What happens in simics (i.e. sunfire machine configuration without timing model) when more than one processor has a memory access to a shared-memory at the same cycle?
What if the access is for the exact location in the shared memory?

Does
simics assume every processor can freely access any memory and location
as if it is only one accessing everything including the bus?

Does memory access requires bus access in simics?
If yes, how does the arbitration happens when multi processors connected to the same bus, performing a memory access?


Thanks,
Cihat.