[Gems-users] profiler

["Dave Z." <zhu_dave@xxxxxxxxx>]

Hello,


Is it possible to keep track of L1 and L2 misses separately in protocols where the L1 and L2 cache controllers are integrated? Could you please show me some pointers?


Thanks,


Dave



      ____________________________________________________________________________________
Looking for last minute shopping deals?  
Find them fast with Yahoo! Search.  http://tools.search.yahoo.com/newsearch/category.php?category=shopping