Re: [Gems-users] error about MOESI_CMP_directory

["Mike Marty" <mike.marty@xxxxxxxxx>]

In this writeback race, the L2 should send a Nack back to the L1.  There should be several examples in MOESI_CMP_directory-L2cache.sm (search for sendWritebackNack or something like that).  Apparnetly the protocol still misses some transitions where a Nack is sent.  Just add a transition and things should work

--Mike

2008/1/18 王佐 <qiushui@xxxxxxxxxx>:

gems-users，您好！

        The following is what I get by loading apache benchmarks only with ruby. My gems version is 2.0, simics version is 2.2.19.

[root@localhost MSI_MOSI_CMP_directory]# cd /home/GEMS/simics/home/MOESI_CMP_directory
[root@localhost MOESI_CMP_directory]# ./simics -stall
Checking out a license... done: commercial license.
Looking for additional Simics modules in ./modules

 +----------------+    Copyright 1998-2005 by Virtutech, All Rights Reserved
 |   Virtutech    |    Version: simics-2.2.19
 |     Simics     |    Compiled: Tue Aug 16 20:22:30 CEST 2005
 +----------------+
   www.simics.com      "Virtutech" and "Simics" are trademarks of Virtutech AB

Type 'copyright' for details on copyright.
Type 'license' for details on warranty, copying, etc.
Type 'readme' for further information about this version.
Type 'help help' for info on the on-line documentation.

simics> read-configuration /home/GEMS/checkpoints/simics-2.x/workloads/apache_warm-16p-65536mb.check
[qlc24B_2 info] Disk registering: Loop id: 0x3
[qlc24B_2 info] Disk registering: Loop id: 0xc
[qlc24B_2 info] Disk registering: Loop id: 0xd
[qlc24B_2 info] Disk registering: Loop id: 0xe
[qlc24B_2 info] Disk registering: Loop id: 0xf
[qlc24B_2 info] Disk registering: Loop id: 0x10
[qlc24B_2 info] Disk registering: Loop id: 0x11
[qlc24B_2 info] Disk registering: Loop id: 0x12
[qlc24B_2 info] Disk registering: Loop id: 0x13
[qlc24B_2 info] Disk registering: Loop id: 0x14
[qlc28B_2 info] Disk registering: Loop id: 0x3
[qlc24B_2 info] Disk registering: Loop id: 0x4
[qlc28B_2 info] Disk registering: Loop id: 0x4
[qlc28B_2 info] Disk registering: Loop id: 0x5
[qlc28B_2 info] Disk registering: Loop id: 0x6
[qlc28B_2 info] Disk registering: Loop id: 0x7
[qlc28B_2 info] Disk registering: Loop id: 0x8
[qlc24B_2 info] Disk registering: Loop id: 0x2
[qlc28B_2 info] Disk registering: Loop id: 0x9
[qlc28B_2 info] Disk registering: Loop id: 0xa
[qlc28B_2 info] Disk registering: Loop id: 0xb
[qlc28B_2 info] Disk registering: Loop id: 0xc
[qlc28B_2 info] Disk registering: Loop id: 0xd
[qlc24B_2 info] Disk registering: Loop id: 0x5
[qlc28B_2 info] Disk registering: Loop id: 0xe
[qlc28B_2 info] Disk registering: Loop id: 0xf
[qlc28B_2 info] Disk registering: Loop id: 0x10
[qlc28B_2 info] Disk registering: Loop id: 0x11
[qlc28B_2 info] Disk registering: Loop id: 0x12
[qlc28B_2 info] Disk registering: Loop id: 0x13
[qlc28B_2 info] Disk registering: Loop id: 0x14
[qlc28B_2 info] Disk registering: Loop id: 0x15
[qlc24B_2 info] Disk registering: Loop id: 0x6
[qlc24B_2 info] Disk registering: Loop id: 0x7
[qlc24B_2 info] Disk registering: Loop id: 0x8
[qlc24B_2 info] Disk registering: Loop id: 0x9
[qlc24B_2 info] Disk registering: Loop id: 0xa
[qlc24B_2 info] Disk registering: Loop id: 0xb
simics> instruction-fetch-mode instruction-fetch-trace
simics> dstc-disable
Turning D-STC off and flushing old data
simics> cpu-switch-time 1
The switch time will change to 1 cycles (for CPU-0) once all processors have synchronized.
simics> load-module ruby
successful installation of the ruby timing model.
simics> ruby0.setparam g_NUM_PROCESSORS 16
simics> ruby0.setparam g_PROCS_PER_CHIP 16
simics> ruby0.setparam g_NUM_L2_BANKS 16
simics> ruby0.setparam g_NUM_MEMORIES 4
simics> ruby0.setparam NUMBER_OF_VIRTUAL_NETWORKS 5
simics> ruby0.setparam g_endpoint_bandwidth 1000
simics> ruby0.init
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
 Processors: 16
Creating system done
Ruby initialization complete
simics> c
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2061: m_id is 0
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2061: m_id is 0
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2062: m_version is 5
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2062: m_version is 5
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2063: g_eventQueue_ptr->getTime() is 7302007
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2063: g_eventQueue_ptr->getTime() is 7302007
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2064: addr is [0x371700c0, line 0x371700c0]
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2064: addr is [0x371700c0, line 0x371700c0]
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2065: event is L1_PUTO
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2065: event is L1_PUTO
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2066: state is OLSX
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2066: state is OLSX
Fatal Error: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2067: Invalid transition
Fatal Error: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2067: Invalid transition
***  Simics getting shaky, switching to 'safe' mode.
***  Simics (main thread) received an abort signal, probably an assertion.

       Can anyone know why? Thanks!

致
礼！


王佐
qiushui@xxxxxxxxxx
2008-01-18

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