[Gems-users] Question about cache and processor parameters for MSI_MOSI_CMP_broadcast


Date: Mon, 11 Feb 2008 01:12:10 -0600
From: "Berkin Ozisikyilmaz" <boz283@xxxxxxxxxxxxxxxxxxxx>
Subject: [Gems-users] Question about cache and processor parameters for MSI_MOSI_CMP_broadcast

Hi,

 

I want to use opal and gems to simulate a 16way cmp machine. I set the number of processors to 16. Then should I change the procs_per_chip and the number_of_chips variables? If I change the number of chips, do I need to change anything about the memory parameters?

 

I also want to modify the cache sizes, so that I can use a smaller dataset for my code (the original input takes too long to simulate and I don’t want to make it fit into caches). Specifically I want to make L1 data cache smaller, while keeping L1 instruction cache original size, and also decreasing L2 cache size. I couldn’t find where details of L1 cache are set in ruby, and I have seen that Opal has some IL1 and DL1 parameters that can be set. However it seems that rubys and opals cache parameters are not related. What should I do? I really appreciate your replies.

 

 

Thanks

Berkin

 

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