Looks like a coherence miss to me. Satisfying a load will get the line in S -- satisfying the store requires the line in M. Hence, both miss.
Regards,
Dan
On Wed, Dec 3, 2008 at 7:39 PM, Ashwath Narasimhan <nashwath@xxxxxxxxx> wrote:
Hi,
I am unable to explain the behavior of RUBY for this scenario. When I Load an address say
0x040 and store data to the same address, the RUBY tool classifies it as a MISS. I am
unable to explain why this is happening. This has nothing to do with my code changes,
since the tool itself lists the total number of misses separately.
Specs: Direct mapped cache,64 byte block size, 64KB L1D and 64KB L1 I cache. MOSI
protocol, Number of processors = 16, 1st column indicates the processor. Tester trace used.
1 0x40000000 0 LD ---> Load 0xXXXXXX00 *****1
1 0x40000001 0 LD
1 0x40000002 0 LD
1 0x40000003 0 LD
1 0x40000064 0 LD
1 0x40000128 0 LD
1 0x40000256 0 LD
1 0x40000257 0 LD
1 0x40000512 0 LD
1 0x40000900 0 LD -----> Load 0xXXXXXX900 *****2
1 0x40000870 0 IFETCH
1 0x40000000 0 ST ----> Should be a HIT ****1
1 0x40000901 0 ST ----> Should be a HIT ****2
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