So for example, I take all the L1 misses to my plug-in another level
of simulator, if that is still a miss, then I'll add 20K cycles, and a
miss will add 2K cycles. You can treat this additional simulator like
last level cache.
-Carole
On Thu, Apr 10, 2008 at 3:16 PM, Dan Gibson <degibson@xxxxxxxx
<mailto:degibson@xxxxxxxx>> wrote:
Under what conditions do you change the latency to 20k? (My guess
about
cancelling the stall time may be incorrect.)
Regards,
Dan
Carole-Jean Wu wrote:
> Going back to the original question,
>
> why if I change my additional latency to be e.g. 20K cycles, the CPI
> starts to make more sense? wouldn't it encounter the same
problem as I
> set it to 20 cycles (e.g. be canceled out) just like what you
> mentioned previously?
>
>
> -Carole
>
> On Thu, Apr 10, 2008 at 3:05 PM, Dan Gibson <degibson@xxxxxxxx
<mailto:degibson@xxxxxxxx>
> <mailto:degibson@xxxxxxxx <mailto:degibson@xxxxxxxx>>> wrote:
>
> Ruby_cycles is incremented by ~1. Not every cycle will have
events, so
> sometimes Ruby_cycles can be logically advanced by more than 1
> cycle at
> a time.
>
> Carole-Jean Wu wrote:
> > Does anyone know for sure that Ruby cycles are incremented
by 1
> or the
> > same orders? Or it is incremented in the order of hundreds or
> > thousands of cycles.
> >
> >
> > Thanks,
> > Carole
> >
> > On Thu, Apr 10, 2008 at 10:13 AM, Dan Gibson
<degibson@xxxxxxxx <mailto:degibson@xxxxxxxx>
> <mailto:degibson@xxxxxxxx <mailto:degibson@xxxxxxxx>>
> > <mailto:degibson@xxxxxxxx <mailto:degibson@xxxxxxxx>
<mailto:degibson@xxxxxxxx <mailto:degibson@xxxxxxxx>>>> wrote:
> >
> > Grep through the code for SIMICS_unstall_proc(). Add a
hack --
> > instead of just un-stalling, call SIMICS_stall_cycle(
> > DESIRED_LATENCY - ELAPSED_LATENCY ).
> >
> >
> > Carole-Jean Wu wrote:
> >> Hello Dan,
> >>
> >> although I still want to take the original miss/hit
latency
> of L1
> >> into account...
> >>
> >>
> >> -Carole
> >>
> >> On Thu, Apr 10, 2008 at 10:05 AM, Dan Gibson
> <degibson@xxxxxxxx <mailto:degibson@xxxxxxxx>
<mailto:degibson@xxxxxxxx <mailto:degibson@xxxxxxxx>>
> >> <mailto:degibson@xxxxxxxx <mailto:degibson@xxxxxxxx>
<mailto:degibson@xxxxxxxx <mailto:degibson@xxxxxxxx>>>> wrote:
> >>
> >> If you want to decide what the latency is (i.e.
not let
> Ruby
> >> proper decide), have a look at what the
> PERFECT_MEMORY_SYSTEM
> >> flag does.
> >>
> >>
> >> Regards,
> >> Dan
> >>
> >> Carole-Jean Wu wrote:
> >>> Hello Dan,
> >>>
> >>> >From my understanding of issueRequest, only cache
> misses go
> >>> there right?
> >>> Do you have suggestions how to tackle this
problem? Why
> >>> would my added latency be canceled out by Ruby's
event
> >>> queue? I tried to increase the latency to e.g. 40000
> >>> something big, and I will start seeing some
variation
> in CPI.
> >>>
> >>> Thanks!
> >>> Carole
> >>>
> >>> On Thu, Apr 10, 2008 at 9:39 AM, Dan Gibson
> >>> <degibson@xxxxxxxx <mailto:degibson@xxxxxxxx>
<mailto:degibson@xxxxxxxx <mailto:degibson@xxxxxxxx>>
> <mailto:degibson@xxxxxxxx <mailto:degibson@xxxxxxxx>
<mailto:degibson@xxxxxxxx <mailto:degibson@xxxxxxxx>>>> wrote:
> >>>
> >>> My first guess is that your latency is
cancelled by
> >>> Ruby's periodic processing of its event
queue. E.g. if
> >>> you stall a request by 10 cycles in the
sequencer,
> then
> >>> Ruby's event queue runs (to simulate the cache
> >>> hierarchy) 2 cycles later, decides the
request was a
> >>> hit, and unstalls the processor, with a net
stall time
> >>> of just 2 cycles.
> >>>
> >>> Regards,
> >>> Dan
> >>>
> >>> Carole-Jean Wu wrote:
> >>>> Hello GEMS-users,
> >>>>
> >>>> I am running into a strange situation when
> simulating a
> >>>> multiprogrammed environment. To make the long
> story short,
> >>>>
> >>>> in Sequencer.C's issueRequest, I am adding
additional
> >>>> latency to "latency" to mimic e.g. a cache hit,
> >>>> latency+=10 and a cache miss, latency+=100.
However,
> >>>> when running two applications with great
> differences on
> >>>> miss ratio, I've find the same CPI in the
> >>>> ruby0.dumpstat file.
> >>>>
> >>>> Can someone explain to me what is going
wrong? Am I
> >>>> inserting this additional latency in the
wrong place?
> >>>>
> >>>>
> >>>> Any help is greatly appreciated!
> >>>>
> >>>> Thanks a lot,
> >>>> Carole
> >>>>
>
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