Re: [Gems-users] "Coherence Ordering for Ring-based Chip Multiprocessors" related

[Mike Marty <mikem@xxxxxxxxxxx>]

If I were able to just send the SLICC .sm files, I would. But 
unfortunately my source tree for the ring-based work has a lot of 
modifications in many Ruby files. One particular challenge was to 
maintain the point-to-point ordering of each ring link when a controller 
could enqueue a message with different latency delay values to model a 
cache lookup latency (this would violate point-to-point ordering). So 
the specification is sort of convoluted in that all enqueue statements 
specify a latency of 1-cycle and that cache access latency is explicitly 
modeled by entering a busy state, scheduling a wakeup XX cycles later, 
and then waking up to leave the busy state and enqueue data with latency 1.
I am traveling this week...when I get back, I will see if it is possibly 
to package these files, but I may not have time given my busy schedule 
this month.
--Mike


曹非 wrote:
> hi
> I have read the paper "Coherence Ordering for Ring-based Chip 
> Multiprocessors" .I want to do some experiments on the ring coherence 
> architectures in the paper. Where can i get the implementation files 
> of the 3 ring coherence architectures in GEMS?Thanks!
> caofei
>
>
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