Re: [Gems-users] The distribution of "total_misses" in ruby stats output

["Lide Duan" <leaderduan@xxxxxxxxx>]

Sorry for the late reply...

I think the problem resides in the profile part of Ruby. When defining action uu_profileMiss in MOESI_CMP_directory-L2cache.sm (I am using MOESI_CMP_directory protocol in my simulation), the last parameter given to function profile_L2Cache_miss() is "machineIDToNodeID(in_msg.Requestor)" which should be the node id of the incoming msg. For example, in a 16p CMP system, if the requestor of the incoming msg is L1Cache-13, machineIDToNodeID() should return 13 as the result so that the corresponding counter in the Profiler (m_perProcTotalMisses[13]) will record this L2 miss.

However, if you look at the function machineIDToNodeID(MachineID machID) in ruby/slicc_interface/RubySlicc_ComponentMapping.h, it returns "machID.num%RubyConfig::numberOfChips()". In the above example, if all the 16p are on a single chip, which means RubyConfig::numberOfChips() equals to 1, machineIDToNodeID will return 13%1 = 0. Actually this function will return 0 for any one of the 16 processors. That's why my simulation results showed the misses only in the 1st processor - the misses of all the processors were totally accumulated to the 1st counter. Obviously, if I place 4p on one chip, the first 4 misses counters in the Profiler will be utilized.

I simply modified the machineIDToNodeID() function in RubySlicc_ComponentMapping.h to return "machID.num", then all the 16 counters correctly reflect the misses on their corresponding processors. I don't know if this can be counted as a little bug of Ruby or not, but if we want to observe the L2 misses on different processors, we have to make that change.

Regards,
Lide

On 8/25/07, Dan Gibson < degibson@xxxxxxxx > wrote:

Good point, Mike. I think the best way to proceed is to put a bunch of printf()'s in Sequencer's makeRequest() function and everything it calls... and figure out where the requests are going... they are certainly getting to the sequencer, but probably not to the L2 caches, where misses are usually profiled.

Regards,
Dan

Mike Marty wrote:

things like user_misses and supervisor_misses should be protocol indepedent

--mike


Dan Gibson wrote:
  

What protocol are you using? Perhaps the protocol is only profiling 
requests from processor 0?

Regards,
Dan

Lide Duan wrote:
    

Dan, the following is just a piece of output I have got:

Processor ID of current request in SimicsDriver::makeRequest() : 8
Processor ID of current request in SimicsProcessor::makeRequest() : 8
Sequencer ID of current request in Sequencer::makeRequest() : 8


Processor ID of current request in SimicsDriver::makeRequest() : 6
Processor ID of current request in SimicsProcessor::makeRequest() : 6
Processor ID of current request in SimicsDriver::makeRequest() : 8

Processor ID of current request in SimicsProcessor::makeRequest() : 8

Sequencer ID of current request in Sequencer::makeRequest() : 8
Processor ID of current request in SimicsDriver::makeRequest() : 6
Processor ID of current request in SimicsProcessor::makeRequest() : 6

Sequencer ID of current request in Sequencer::makeRequest() : 6

Processor ID of current request in SimicsDriver::makeRequest() : 8
Processor ID of current request in SimicsProcessor::makeRequest() : 8
Sequencer ID of current request in Sequencer::makeRequest() : 8


Other processor IDs also appeared besides the above, so I think 

SimicsDriver, SimicsProcessor and Sequencer all see the requests from 
all the processors.

Lide


On 8/25/07, *Dan Gibson* < 

degibson@xxxxxxxx 
<mailto:degibson@xxxxxxxx>> wrote:

    Sequencer identifiers are:


    (m_chip_ptr->getID()*RubyConfig::numberOfProcsPerChip()+m_version)


    Regards,
    Dan

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