Re: [Gems-users] SINGLE_ACCESS_L2_BANKS Usage

[Mike Marty <mikem@xxxxxxxxxxx>]

> Thanks Mike.
> I was considering the events in cache controller itself.
> I am using MSI_MOSI_CMP_directory protocol.  From the protocol file one 
> transition
> transition(L2_SS, {L1_GETS, L1_GET_INSTR}) {
>   set_setMRU;
>   ww_profileMissNoDir;
>   nn_addSharer;
>   k_dataFromL2CacheToL1Requestor;
>   jj_popL1RequestQueue;
> }
> That means, the cache line is not moving to transient state and the data from 
> L2 is enqueued at output port of L2 controller after L2_RESPONSE_LATENCY 
> cycles, right?
Yes (assuming L2_RESPONSE_LATENCY is indeed used in 
k_dataFromL2CacheToL1Requestor)
> And it also seems it will allow to serve another GETS coming 
> in the next cycle and the data for that will be in output port of cache 
> controller at L2_RESPONSE_LATENCY+1 cycle from current cycle. Am I right?
Yes

> And if that is the case then it seems the cache is assumed pipelined, right?
Yes

--Mike