Re: [Gems-users] L1 cache misses in Gems

[Mike Marty <mikem@xxxxxxxxxxx>]

The transition from M_W to MM_W keeps track if the block has been 
written to.  This is used to implement the migratory sharing optimization.
A similar transition, in any MESI protocol, if you transition from state 
E to state M.
Should these be treated as L1 "misses".  Not really.  Do they require 
modification of the coherence state?  Absolutely.
--Mike


Yoav Etsion wrote:
> Hi,
>
> I'm analyzing cache behavior on a CMP (MOESI_CMP_directory, Gems-2.0,
> Simics 3.0.27), and
> for that purpose I have added a statistics module to Gems that is
> called on every cache insertion,
> access, and eviction.
>
> When counting the number of L1 cache misses, I've found some
> discrepancies between the number
> of cache misses my code counts, and the ones counted by Gems - which
> seem to be caused
> by different definitions of a cache miss. My approach is that a block
> that resides in the cache with
> proper permissions to perform the required action is a hit.
> However, Gems treats writes to dirty cache-resident blocks as a miss -
> for example, a transition
> from M_W to MM_W.
>
> What is your reason for treating such accesses as misses?
> (or in other words - am I missing something?)
>
> Thanks,
>
> Yoav
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