Re: [Gems-users] How to identify cache hit rate in Ruby?

["Lei Yang" <lei.d.yang@xxxxxxxxx>]

Hi Dave,

Thanks a lot for your reply. I'll try modify the sequencer and get the
hit and miss counts. It's a pity ruby doesn't already provide such
statistics, especially when we want to compare with results in other
work, which used miss/hit rate instead of misses per thousand
instructions. I'll let you know if I get similar results like you.

Perhaps the GEMS author would know about how to do this correctly, and
why it is not already done?

Thank you!

Lei

On 11/1/07, Dave Z. <zhu_dave@xxxxxxxxx> wrote:
> Lei,
>
> I'm trying to find out the cache hit/miss rate, but
> haven't had any luck yet. I've modified
> Sequencer::makeRequest to keep track of hits and
> misses, but for some reason the number of hits and
> misses tracked by the Sequencer is totally different
> that the ones profiled by Ruby. Perhaps Ruby profiles
> the hits/misses on conditions that are not tracked by
> the Sequencer. I have no idea. So, you can try a
> similar approach and see if it works for you.
>
> Regards,
>
> Dave
>
>
> --- Lei Yang <lei.d.yang@xxxxxxxxx> wrote:
>
> > Dear list,
> >
> > I'm wondering whether Ruby provides such statistics
> > like cache
> > hit/miss rate? For example, in the following stats
> > report from Ruby:
> >
> > L1D_cache cache stats:
> >  L1D_cache_total_misses: 29807
> >  L1D_cache_total_demand_misses: 29807
> >  L1D_cache_total_prefetches: 0
> >  L1D_cache_total_sw_prefetches: 0
> >  L1D_cache_total_hw_prefetches: 0
> >  L1D_cache_misses_per_transaction: 29807
> >  L1D_cache_misses_per_instruction: 0.000143247
> >  L1D_cache_instructions_per_misses: 6980.94
> >
> >  L1D_cache_request_type_LD:   16.0197%
> >  L1D_cache_request_type_ST:   82.7557%
> >  L1D_cache_request_type_ATOMIC:   1.22454%
> >
> >  L1D_cache_access_mode_type_SupervisorMode:   6933
> >  23.2596%
> >  L1D_cache_access_mode_type_UserMode:   22874
> > 76.7404%
> >  L1D_cache_request_size: [binsize: log2 max: 64
> > count: 29807 average:
> > 4.90469 | standard deviation: 4.44371 | 0 642 88
> > 23854 5077 0 0 146 ]
> >
> > We know the total L1D cache misses, and the
> > misses_per_instruction.
> > But do we know the total number of cache acesses,
> > and thus the
> > hit/miss rate? Also, what does
> > misses_per_transaction mean?
> >
> > Thank you in advance!
> > Lei
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