[Gems-users] TLB misses, Ruby and Simics

[mehmetderin.harmanci@xxxxxxx]

 Hello,

 I have a question about how the exceptions/traps are managed by Simics+Ruby.
 My main concern is to filter out (in Ruby) the TLB miss related address
 requests arriving from Simics (I'm simulating another TLB and another TLB
 miss handler which does not act on the same addresses as the Simics TLB/MMU).
 But there is a subtle issue that I could not understand. I would appretiate
 if anybody could help me on that issue.

 I would explain what happens and what I do not understand in the story.
 First of all, since I would like to filter out the TLB miss related
 addresses arriving from Simics, I would like to avoid the repetition of
 the faulting address due to the TLB miss. While I was trying to do this
 I was confused which access of the faulting address (the one before the TLB
 miss or after the TLB miss) I should filter out to carry out the  cache
 simulation for the faulting address as if it arrived only once and as if
 there were no TLB misses.

 My observation is as follows:

 When the faulting address arrives it is first passed to Ruby by Simics and
 Ruby starts handling it as if it is not faulting. After Ruby returns (here
 what I mean by returning is giving the control to Simics and probably this
 does not mean returning the latency due to that address to Simics), Simics
 finds the TLB miss out and sends the TLB miss handler instruction address
 to Ruby 1 cycle later (I think this happens independent of whether the
 access is intruction or data access, but I'm not 100% sure).

 The question is: If there were a miss with the faulting address would the
 cache simulation be carried out for the fauting address or, the cache access
 of the faulting address is somehow cancelled out or overriden by the arriving
 TLB miss handling instruction access? Does this mean that for a faulting
 address we will pass always 1 simics cycle before jumping to the TLB miss
 handler and thus is it more suitable to filter out this access (the access
 before TLB miss handler) of the faulting address for simulating its access to
 the caches?

 I was not sure if this is a message targetted to this forum or Simics forum
 but I think the issue is more related to how Ruby interacts with Simics to
 act on a TLB miss.

 Any help for clarifying the issue will be appretiated.

   Thanks,

      Derin Harmanci