[Gems-users] The Network in Ruby

["Lide Duan" <leaderduan@xxxxxxxxx>]

Hi there,

I am trying to do something with the interconnect in Ruby, but I have encountered some problems:

1. What's the difference between intra-chip and inter-chip networks? There are 4 "auto-generated" networks in Ruby, but the tutorial says they are used in "inter-chip". If I just simulate a single chip with 8 processors, is there any "inter-chip"  network?
    According to the Figure of Ruby, seems that there is only one network connecting all the components including L1s, L2 banks and directories which are the memories. So I guess the interconnect treats all the components equally and connects them with switches and links. If so, how does it distinguish intra-chip or inter-chip? Meaning, does it apply the different parameters ( e.g. ON_CHIP_LINK_LATENCY, NETWORK_LINK_LATENCY) to different links as those links may be intra- or inter- chip?

2. About the 4 auto-generated networks, I have run a checkpoint loading Ruby with each of them for 1000000 SIMICS cycles, and I've got different results. For the link latency, CROSSBAR has a constant latency 152 between each pair of components, while HIERARCHICAL_SWITCH has a constant latency of 356. Why does HIERARCHICAL_SWITCH also have a constant latency? Is it because all the packets have to go through the root switch even though the source and destination are neighbours?

    In PT_TO_PT, the latencies may be 3, 52 or 101 because of the different on-chip and off-chip latencies set in rubyconfig.defaults, but the TORUS_2D has the exactly same latency of each component pair with PT_TO_PT, why?
 

3. I also set g_PRINT_TOPOLOGY true to see the results in the output file. PT_TO_PT has a switch0 with 48 in-links and 48 out-links, a switch1 with 1 in-link and 1 outlink, and switch2 to switch 31 with 0 in-link and 0 out-link. How can I understand this? Also, TORUS_2D has a switch0 with 52 in-links and 52 out-links, but switch1 to switch 15 each has 4 in-links and 4 out-links, why? Is there anyway I can understand the built-in topologies easier?

 

Thanks a lot,

Lide