[Gems-users] A question in LogTM

[郭锐 <timmyguo@xxxxxxxxxxxxxxxx>]

When an ld_xact/st_xact hits in a fast path, the request never goes to Cache
Controller. The question is that, in such a situation, how the simulator
sets up the R/W bit for the corresponding cache line? It seems that the
simulator leaves the flag unchanged--be a big bug? If the problem do exists,
how to get a quick fix?

G.R.