Hi,
Happy new year ;)...
I'm trying to get a trace of memory accesses (L2 cache misses) for a
benchmark, especially the physical address of each L2 cache miss.
Right now what I found is that Ruby only records the number of misses.
The process is like: in some .sm protocol file,
profile_L2Cache_miss(defined in
ruby/slicc_interface/RubySlicc_Profiler_interface.c) is called.
Eventually, the profiling work for L2 misses is done at addL2StatSample
method.
m_perProcTotalMisses[id]++;
.....
It records the number of L2 misses for each processor. It is not clear
to me how to keep track of the physical address for each L2 miss.
Any advice is really appreciated.
-Wei
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