Re: [Gems-users] MOSI_SMP_bcast : inclusion between L1 and L2

[Mike Marty <mikem@xxxxxxxxxxx>]

I can't say for sure how feasible this is for the single-controller 
protocols.  It might be possible, but I haven't put much thought into 
it.  Pay attention to getState/setState and the replacement functions.  
There are numerous assertions that check the exclusion property. 

MSI_MOSI_CMP_directory enforces strict L1/L2 inclusion, but the L2 is 
shared.  Nonetheless, you could just use this protocol with 
PROCS_PER_CHIP set to 1. 

--Mike



avadh patel wrote:
> Hi everyone,
>
> I have been studying MOSI_SMP_bcast protocol and I found out that in this
> protocol, it doesn't maintain the inclusion property between L1 and L2,
> instead they maintain exclusion property. So, if line is in L1 cache 
> it cant
> be in L2 cache and coherence state is maintained in both level caches.
> Please correct me if I am wrong.
>
> I would like to change this property to make it inclusive. Is there any
> simple and faster way to change MOSI_SMP_bcast to have inclusion 
> property?
> What should I consider when doing this changes because I am very much 
> new to
> this slicc language.
>
> Thanks in advance.
>
> - Avadh Patel
>
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