Re: [Gems-users] Shared Memory Bus

[Nawab Ali <alin@xxxxxxxxxxxxxxxxxx>]

Mike Marty wrote:
Thank you Mike for the quick response.
> Simics-x86 does not allow GEMS to model instruction fetches.
Does this mean that I can't use Ruby with x86 target machines??

-nawab

> GEMS can simulate a wide variety of interconnect configurations, and it can
> model/measure memory bandwidth.  However it does not do a shared-wire bus
> without modifications.
>
> --Mike
>
>
> > Hi,
> > I'm trying to simulate a 2-core CMP with split, private L1 caches and a
> > shared, unified L2 cache using the Virtutech Simics simulator. My
> > simulated architecture is a x86 machine (enterprise. Red Hat Linux 7.3).
> >
> > I just found out that Simics by default does not model a memory bus. As
> > part of my research, I'm trying to measure the memory bandwidth of a CMP
> > as a function of the number of cores. Therefore, I have to model a
> > memory bus along with the bus contention.
> >
> > My question is, does GEMS/Ruby model a shared memory bus by default??
> > I'm new to the GEMS simulator, so I'd appreciate any help on this.
> >
> > Thank you
> > nawab
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--
Nawab Ali.
The Ohio State University.
http://www.cse.ohio-state.edu/~alin