Re: [Gems-users] Fwd: L1 miss breakdown

[Mike Marty <mikem@xxxxxxxxxxx>]

One technique I've used is to modify hh_store_hit and h_load_hit in the L1
controller to pass back which component (memory, local L2, remote L2, etc)
that satisfied the request.  Then profile this.

--Mike

>
>  Hello,
>
>    I sent this message earlieri but I'm resending it. I'm really missing
>   some point and need some help (some pointers maybe).
>
>        Derin Harmanci
>
>
>
> ----- Forwarded message from mehmetderin.harmanci@xxxxxxx -----
>     Date: Thu, 21 Sep 2006 15:21:25 +0200
>     From: mehmetderin.harmanci@xxxxxxx
> Reply-To: Gems Users <gems-users@xxxxxxxxxxx>
>  Subject: [Gems-users] L1 miss breakdown
>       To: Gems Users <gems-users@xxxxxxxxxxx>
>
>
>
>    Hello all,
>
>       I'm trying to understand the MSI_MOSI_CMP_directory protocol. My main
>    objective is actually to have a breakdown of L1 misses, the breakdown
>    being local L2 hit, remote L2 hit and on-chip miss (off-chip hit).  I
>    assume all L2 misses correspond to on-chip misses, however to distinguish
>    if an L2 hit is local or remote I need to figure out at what points
>    exactly an L2 hit occur. I took the following path but it did not help
>    me too much. I found out all the actions of L2 cache controller where the
>    DataBlk is read from the L2 cache directly (as if the data was already
>    in the L2 cache and it was found in the cache). However there are about
>    ten of these functions and I'm a little bit lost in the protocol to
>    understand what they do exactly. Is there a way to filter out these
>    functions (i.e. to figure out which correspond to actual L2 hits)? Or
>    I should look transition by transition to figure out the actual hits?
>    Does anybody have an idea how to do the breakdown, if the above is too
>    complicated? I'll really appretiate any help, since I've been working on
>    this for quite a time and I do not find a way yet.
>
>       Thanks,
>
>         Derin Harmanci.
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