[Gems-users] state transitions

["Dave Z." <zhu_dave@xxxxxxxxx>]

Hello,

I'm looking into MOESI_SMP_hammer's state transitions
and trying to figure out a transition diagram for
certain conditions as I'm interested in analyzing the
coherence behavior of my benchmarks. But I get
confused a little bit. Let's say that we will bring
data to the cache, modify it, and then another
processor will issue a read request. On an AMD
Opteron, this would be something like: E -> M -> O.
Initially, the cache line will be in exclusive state.
When it's modified, it will be in modified state. On a
read request from another processor, it will be in
owned state. Looking at the state transitions in
MOESI_SMP_hammer, initially the data will be in I
state and a cache block will be allocated. Modifying
the data (GETX) will put it into IM state. But there
is no way out from IM state, in other words, there is
no load/store transition from IM state. So, I'm not
sure if I understand the transitions well. Could
somebody please tell me what I'm missing? Your
comments will be greatly appreciated.

Thank you.

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