Re: [Gems-users] regd ruby results and magic instruction

[Nauman Rafique <nrafique@xxxxxxxxxx>]

I vaguely remember coming across a similar problem. I think some CMP protocols
use chip id when profiling misses. If you are simulating only one chip, all
misses would be profiled for node 0. You have to trace your way back from
function Profiler::addL2StatSample to the SLICC code and see if thats the problem.

-- 
Nauman Rafique
Purdue University


Quoting "Dave Z." <zhu_dave@xxxxxxxxx>:

> 
> 
> --- Dan Gibson <degibson@xxxxxxxx> wrote:
> 
> > Dave Z. wrote:
> 
> > >> Using non-sarek
> > >> targets or even sarek 
> > >> targets with some configuration options set can
> > >> result in more than on 
> > >> physical memory object (often one per processor).
> > >> Ruby installs itself 
> > >> of "phys_mem0", which can manifest as only
> > showing
> > >> accesses from cpu0. 
> > >> Find out if a "phys_mem0" object exists in your
> > >> simulation, and also a 
> > >> "phys_mem1", "phys_mem2", etc.
> > >>     
> > >
> > > There exists only phys_mem0 object. What do I need
> > to
> > > do to have phys_mem1? Perhaps private L1 cache and
> > > shared L2 cache? I would like to see memory
> > accesses
> > > from each processor. 
> > >
> > >   
> > You DON'T want separate phys_mems...it just
> > complicates things.
> > >> Otherwise, have you set the cpu-switch-time in
> > >> Simics to 1? 
> > >>     
> > >
> > > No, I haven't. The current CPU switch time is
> > 1000000
> > > cycles.
> > >
> > >   
> > THAT is the problem then. Simics is running for very
> > few instructions 
> > and isn't even running processor 1 at all during
> > your benchmark. Use 
> > cpu-switch-time 1 (and simulate for at least 1000000
> > cycles to allow the 
> > switch to occur) and your problem will go away.
> 
> I set the cpu-switch-time to 1. But I got
> total_misses: 142986 [142986 0]. (Ruby_cycles:
> 150973229) What else could be the problem?
> 
> Thank you for your help.
> 
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