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| Date: | Sat, 28 Oct 2006 10:25:25 +0200 |
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| From: | "Daniele Bordes" <daniele.bordes@xxxxxxxxx> |
| Subject: | Re: [Gems-users] CPU accesses to L2 cache |
Thank you for your quick and exhaustive reply, Nauman. The fact is that 99% of CPU0 misses in L2 are supervisor misses. |
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