Since this is frequently asked, I put an answer on our Wiki:
http://www.cs.wisc.edu/gems/doc/wiki/moin.cgi/Frequently_Asked_Questions
--Mike
> Is it possible in ruby to change the access times of the caches that I configure?
>
> I tried a simple experiment. I ran enterprise-common.simics with $num_cpus=4. I defined a 16KB ICache and 16KB DCache for each processor. I used MOSI_SMP_bcast as the cache coherence protocol. Now, I want to set the time to access instruction/data from L1 Cache. Is it possible similarly to change the access time of data from memory, for example can I specify to simics/ruby that data access time from main memory is not 700 cycles but 850 cycles?
>
> Thanks,
> Kushal.
>
>
> -----Original Message-----
> From: gems-users-bounces@xxxxxxxxxxx on behalf of Dave Z.
> Sent: Tue 11/21/2006 2:57 PM
> To: gems Users
> Subject: [Gems-users] ruby results
>
> Hi,
>
> I've upgraded my Simics version to 3.0.22. Everything
> seems to work fine except for the Ruby results. I'm
> not sure if this is a GEMS problem, but the results I
> get regarding the memory requests (misses, coherence
> events, etc.) are all zero. After reading my
> checkpoint, I do the following:
>
> instruction-fetch-mode instruction-fetch-trace
> istc-disable
> dstc-disable
> cpu-switch-time 1
> magic-break-enable
> load-module ruby
> ruby0.init
>
> The only thing different from my old configuration is
> that I get a warning info as follows:
>
> [cpu0 info] Note that on this cpu,
> instruction-fetch-trace is implemented using
> instruction-cache-access-trace with a suitable cache
> line size.
> [cpu1 info] Note that on this cpu,
> instruction-fetch-trace is implemented using
> instruction-cache-access-trace with a suitable cache
> line size.
>
> The Simics folks say that it's a harmless info message
> and the simulation results shouldn't change.
>
> Am I missing something? Has anyone had the same
> problem before?
>
> Thanks for your help!
>
>
>
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