Thanks Luke,
I will try the C code solution as I need both modules loaded.
Regards,
Nikolas
Quoting Luke Yen <lyen@xxxxxxxxxxx>:
> Hi Nikolas,
>
> The way to do this is to register an exception callback so that Simics
> can inform you whenever it is about to take an exception, and when
> the exception completes:
>
> SIM_hap_register_callback("Core_Exception", (cb_func_no_t)
> ctrl_exception_start, (void *) NULL);
> SIM_hap_register_callback("Core_Exception_Return", (cb_func_no_t)
> ctrl_exception_done, (void *) NULL);
>
> You can do this using a Python script (independent of Opal or Ruby,
> useful if you just want to profile without loading those modules). or do
> this using C code in Ruby or Opal.
>
> Then Simics will call ctrl_exception_start() before each exception
> (including TLB),
> and ctrl_exception_done() after each exception completes. Arguments for
> the callback functions are:
>
> void ctrl_exception_start(void* desc, void* cpu, integer_t val)
>
> where val is the exception number. Again you can implement the callback
> functions in python or C code.
>
> Regards,
> Luke
>
> On Mon, 20 Nov 2006 nikolaos@xxxxxxxxxx wrote:
>
> >
> >
> > Hi all,
> >
> > I need to trace TLB misses (both D-TLB and I-TLB), and searching through
> the
> > source code I found the pseq_t::postException function. Would it be correct
> to
> > use this function to trace when the Fast_Data_Access_MMU_Miss (0x68) and
> > Fast_Instruction_Access_MMU_Miss (0x64) exceptions happen? Is
> postException
> > called for all exceptions that happen in Opal-Ruby?
> >
> > Thanks a lot,
> >
> > Nikolas Galanis
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