I'm using GEMS with the DNUCA configuration, as described by the
CMP-NUCA page in the Wiki. I'd like to run it with
PERFECT_DNUCA_SEARCH off, but it looks to me like there may be some
coherence problems with this configuration.
It runs, but I'm seeing some situations where the same block is in
multiple L2 caches at once. This doesn't to seem to match my
understanding of how things should work when ENABLE_REPLICATION is
off. I figure that two at a time might be normal during migration,
but I've seen three or more at once.
So, my main question is: should DNUCA work with the perfect search
turned off? Do my observations indicate a problem or are they normal?
The way I discovered this problem was to add some code to the
'imperfect' search that also scans the tag array of each pertient L2,
much like the perfect search code. It simply counts the number of L2s
for which isBlockInBank(L2Cache, addr) returns true. I have attached
the .py file I'm using, as well at the debugging information for an
address that shows up in three L2s at once.
--
/-----------------------------------------------------------
| Robert P Ricci <ricci@xxxxxxxxxxx> | <ricci@xxxxxxxxxxxxx>
| Research Associate, University of Utah Flux Group
| www.flux.utah.edu | www.emulab.net
\-----------------------------------------------------------
303500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
303504 0 7 L1Cache Load NP>IS [0x9b48040, line 0x9b48040]
303510 0 113 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303512 0 241 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303512 0 225 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303518 0 129 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303518 0 177 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303518 0 161 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303518 0 145 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303520 0 193 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303520 0 209 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303526 0 7 Collector Miss_Get Col_NP>Col_P [0x9b48040, line 0x9b48040]
303528 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
303528 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
303530 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
303530 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
303530 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
303532 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
303534 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
303534 0 7 Collector Miss_Get_last Col_P>Col_P [0x9b48040, line 0x9b48040]
303535 0 7 Collector Issue_L2_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
303546 0 81 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303546 0 17 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303546 0 49 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303548 0 97 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303548 0 65 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303552 0 1 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303552 0 33 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
303562 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
303562 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
303562 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
303566 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
303566 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
303574 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
303574 0 7 Collector Miss_Get_final Col_P>Col_NP [0x9b48040, line 0x9b48040]
303575 0 7 Collector Issue_Dir_Get Col_NP>Col_NP [0x9b48040, line 0x9b48040]
303618 0 1 Directory GETS M>NO [0x9b48040, line 0x9b48040]
303729 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 229 cycles Directory No
303729 0 7 L1Cache Data_All_Tokens IS>M_W [0x9b48040, line 0x9b48040] Directory-1
303730 0 7 L1CacheSend_Register_wo_Tokens M_W>M_W [0x9b48040, line 0x9b48040]
303747 0 209 L2Cache Register_wo_Tokens L2_NP>L2_AS [0x9b48040, line 0x9b48040]
303779 0 7 L1CacheUse_TimeoutNoStarvers M_W>M [0x9b48040, line 0x9b48040]
371000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
371004 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
371004 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
381000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
381004 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
381004 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
402500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
402504 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
402504 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
406000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
406004 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
406004 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
415000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
415004 7 -1 Seq Done > [0x9b48050, line 0x9b48040] 4 cycles L1Cache No
415004 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
418500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
418504 7 -1 Seq Done > [0x9b48048, line 0x9b48040] 4 cycles L1Cache No
418504 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
419000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
419004 7 -1 Seq Done > [0x9b48058, line 0x9b48040] 4 cycles L1Cache No
419004 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
422504 0 7 L1Cache L1_Replacement M>I [0x9b48040, line 0x9b48040]
422511 0 113 L2CacheWriteback_All_Tokens L2_NP>L2_M [0x9b48040, line 0x9b48040]
500000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
500004 0 7 L1Cache Store NP>IM [0x9b48040, line 0x9b48040]
500010 0 113 L2Cache L1_GETX L2_M>L2_AS [0x9b48040, line 0x9b48040]
500012 0 241 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
500012 0 225 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
500018 0 129 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
500018 0 145 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
500018 0 161 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
500018 0 177 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
500020 7 -1 Seq Done > [0x9b48068, line 0x9b48040] 20 cycles L2Cache No
500020 0 7 L1Cache Data_All_Tokens IM>MM_W [0x9b48040, line 0x9b48040] L2Cache-113
500020 0 193 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
500020 0 209 L2Cache L1_GETX L2_AS>L2_AS [0x9b48040, line 0x9b48040]
500021 0 7 L1Cache Drop_Registration MM_W>MM_W [0x9b48040, line 0x9b48040]
500026 0 7 Collector Miss_Get Col_NP>Col_P [0x9b48040, line 0x9b48040]
500028 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
500028 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
500030 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
500030 0 7 Collector Hit_Get Col_P>Col_F [0x9b48040, line 0x9b48040]
500030 0 7 Collector Hit_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
500032 0 7 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
500034 0 7 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
500034 0 7 Collector Miss_Get_last Col_F>Col_NP [0x9b48040, line 0x9b48040]
500070 0 7 L1CacheUse_TimeoutNoStarvers MM_W>MM [0x9b48040, line 0x9b48040]
501000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
501004 7 -1 Seq Done > [0x9b48070, line 0x9b48040] 4 cycles L1Cache No
501004 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
506000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
506004 7 -1 Seq Done > [0x9b48050, line 0x9b48040] 4 cycles L1Cache No
506004 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
508500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
508504 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
508504 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
509500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
509504 7 -1 Seq Done > [0x9b48040, line 0x9b48040] 4 cycles L1Cache No
509504 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
512500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
512504 7 -1 Seq Done > [0x9b48048, line 0x9b48040] 4 cycles L1Cache No
512504 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
513000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
513004 7 -1 Seq Done > [0x9b48058, line 0x9b48040] 4 cycles L1Cache No
513004 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
515500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
515504 7 -1 Seq Done > [0x9b48048, line 0x9b48040] 4 cycles L1Cache No
515504 0 7 L1Cache Store MM>MM [0x9b48040, line 0x9b48040]
516000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
516004 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
516004 0 7 L1Cache Store MM>MM [0x9b48040, line 0x9b48040]
680000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
680004 7 -1 Seq Done > [0x9b48040, line 0x9b48040] 4 cycles L1Cache No
680004 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
681000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
681004 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
681004 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
717000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
717004 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
717004 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
769500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
769504 7 -1 Seq Done > [0x9b48040, line 0x9b48040] 4 cycles L1Cache No
769504 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
778500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
778504 7 -1 Seq Done > [0x9b48040, line 0x9b48040] 4 cycles L1Cache No
778504 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
803000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
803004 7 -1 Seq Done > [0x9b48040, line 0x9b48040] 4 cycles L1Cache No
803004 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
841000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
841004 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
841004 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
889500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
889504 7 -1 Seq Done > [0x9b48040, line 0x9b48040] 4 cycles L1Cache No
889504 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
890500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
890504 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
890504 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
903500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
903504 7 -1 Seq Done > [0x9b48040, line 0x9b48040] 4 cycles L1Cache No
903504 0 7 L1Cache Load MM>MM [0x9b48040, line 0x9b48040]
938504 0 7 L1Cache L1_Replacement MM>I [0x9b48040, line 0x9b48040]
938511 0 113 L2CacheWriteback_All_Tokens L2_AS>L2_M [0x9b48040, line 0x9b48040]
1022500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1022504 0 7 L1Cache Load NP>IS [0x9b48040, line 0x9b48040]
1022510 0 113 L2Cache L1_GETS L2_M>L2_AS [0x9b48040, line 0x9b48040]
1022512 0 225 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1022512 0 241 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1022518 0 161 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1022518 0 177 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1022518 0 129 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1022518 0 145 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1022520 0 193 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1022520 0 209 L2Cache L1_GETS L2_AS>L2_AS [0x9b48040, line 0x9b48040]
1022520 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 20 cycles L2Cache No
1022520 0 7 L1Cache Data_All_Tokens IS>M_W [0x9b48040, line 0x9b48040] L2Cache-113
1022521 0 7 L1Cache Drop_Registration M_W>M_W [0x9b48040, line 0x9b48040]
1022526 0 7 Collector Miss_Get Col_NP>Col_P [0x9b48040, line 0x9b48040]
1022528 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
1022528 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
1022530 0 7 Collector Hit_Get Col_P>Col_F [0x9b48040, line 0x9b48040]
1022530 0 7 Collector Hit_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1022530 0 7 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1022532 0 7 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1022534 0 7 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1022534 0 7 Collector Miss_Get_last Col_F>Col_NP [0x9b48040, line 0x9b48040]
1022570 0 7 L1CacheUse_TimeoutNoStarvers M_W>M [0x9b48040, line 0x9b48040]
1211000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1211004 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
1211004 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
1213000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1213004 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
1213004 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
1233500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1233504 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
1233504 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
1308000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1308004 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
1308004 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
1402500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1402504 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
1402504 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
1490500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1490504 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
1490504 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
1564000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1564004 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 4 cycles L1Cache No
1564004 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
1747000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1747004 7 -1 Seq Done > [0x9b48040, line 0x9b48040] 4 cycles L1Cache No
1747004 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
1859000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1859004 7 -1 Seq Done > [0x9b48040, line 0x9b48040] 4 cycles L1Cache No
1859004 0 7 L1Cache Load M>M [0x9b48040, line 0x9b48040]
1945004 0 7 L1Cache L1_Replacement M>I [0x9b48040, line 0x9b48040]
1945011 0 113 L2CacheWriteback_All_Tokens L2_AS>L2_M [0x9b48040, line 0x9b48040]
1946500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1946504 0 7 L1Cache Store NP>IM [0x9b48040, line 0x9b48040]
1946510 0 113 L2Cache L1_GETX L2_M>L2_AS [0x9b48040, line 0x9b48040]
1946512 0 225 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1946512 0 241 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1946518 0 177 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1946518 0 129 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1946518 0 161 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1946518 0 145 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1946520 0 209 L2Cache L1_GETX L2_AS>L2_AS [0x9b48040, line 0x9b48040]
1946520 0 193 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1946520 7 -1 Seq Done > [0x9b48070, line 0x9b48040] 20 cycles L2Cache No
1946520 0 7 L1Cache Data_All_Tokens IM>MM_W [0x9b48040, line 0x9b48040] L2Cache-113
1946521 0 7 L1Cache Drop_Registration MM_W>MM_W [0x9b48040, line 0x9b48040]
1946526 0 7 Collector Miss_Get Col_NP>Col_P [0x9b48040, line 0x9b48040]
1946528 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
1946528 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
1946530 0 7 Collector Hit_Get Col_P>Col_F [0x9b48040, line 0x9b48040]
1946530 0 7 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1946530 0 7 Collector Hit_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1946532 0 7 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1946534 0 7 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1946534 0 7 Collector Miss_Get_last Col_F>Col_NP [0x9b48040, line 0x9b48040]
1946570 0 7 L1CacheUse_TimeoutNoStarvers MM_W>MM [0x9b48040, line 0x9b48040]
1956504 0 7 L1Cache L1_Replacement MM>I [0x9b48040, line 0x9b48040]
1956511 0 113 L2CacheWriteback_All_Tokens L2_AS>L2_M [0x9b48040, line 0x9b48040]
1958000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1958004 0 7 L1Cache Load NP>IS [0x9b48040, line 0x9b48040]
1958010 0 113 L2Cache L1_GETS L2_M>L2_AS [0x9b48040, line 0x9b48040]
1958012 0 241 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1958012 0 225 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1958018 0 161 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1958018 0 129 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1958018 0 145 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1958018 0 177 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1958020 7 -1 Seq Done > [0x9b4804c, line 0x9b48040] 20 cycles L2Cache No
1958020 0 7 L1Cache Data_All_Tokens IS>M_W [0x9b48040, line 0x9b48040] L2Cache-113
1958020 0 209 L2Cache L1_GETS L2_AS>L2_AS [0x9b48040, line 0x9b48040]
1958020 0 193 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1958021 0 7 L1Cache Drop_Registration M_W>M_W [0x9b48040, line 0x9b48040]
1958026 0 7 Collector Miss_Get Col_NP>Col_P [0x9b48040, line 0x9b48040]
1958028 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
1958028 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
1958030 0 7 Collector Hit_Get Col_P>Col_F [0x9b48040, line 0x9b48040]
1958030 0 7 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1958030 0 7 Collector Hit_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1958032 0 7 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1958034 0 7 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1958034 0 7 Collector Miss_Get_last Col_F>Col_NP [0x9b48040, line 0x9b48040]
1958070 0 7 L1CacheUse_TimeoutNoStarvers M_W>M [0x9b48040, line 0x9b48040]
1980504 0 7 L1Cache L1_Replacement M>I [0x9b48040, line 0x9b48040]
1980511 0 113 L2CacheWriteback_All_Tokens L2_AS>L2_M [0x9b48040, line 0x9b48040]
1985500 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1985504 0 7 L1Cache Store NP>IM [0x9b48040, line 0x9b48040]
1985510 0 113 L2Cache L1_GETX L2_M>L2_AS [0x9b48040, line 0x9b48040]
1985512 0 241 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1985512 0 225 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1985518 0 177 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1985518 0 161 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1985518 0 145 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1985518 0 129 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1985520 0 193 L2Cache L1_GETX L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1985520 7 -1 Seq Done > [0x9b48060, line 0x9b48040] 20 cycles L2Cache No
1985520 0 7 L1Cache Data_All_Tokens IM>MM_W [0x9b48040, line 0x9b48040] L2Cache-113
1985520 0 209 L2Cache L1_GETX L2_AS>L2_AS [0x9b48040, line 0x9b48040]
1985521 0 7 L1Cache Drop_Registration MM_W>MM_W [0x9b48040, line 0x9b48040]
1985526 0 7 Collector Miss_Get Col_NP>Col_P [0x9b48040, line 0x9b48040]
1985528 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
1985528 0 7 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
1985530 0 7 Collector Hit_Get Col_P>Col_F [0x9b48040, line 0x9b48040]
1985530 0 7 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1985530 0 7 Collector Hit_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1985532 0 7 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1985534 0 7 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1985534 0 7 Collector Miss_Get_last Col_F>Col_NP [0x9b48040, line 0x9b48040]
1985570 0 7 L1CacheUse_TimeoutNoStarvers MM_W>MM [0x9b48040, line 0x9b48040]
1989378 0 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1989382 0 0 L1Cache Load NP>IS [0x9b48040, line 0x9b48040]
1989388 0 1 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1989390 0 129 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1989390 0 145 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1989392 0 241 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1989396 0 225 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1989398 0 161 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1989398 0 177 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1989400 0 193 L2Cache L1_GETS L2_NP>L2_NP [0x9b48040, line 0x9b48040]
1989400 0 209 L2Cache L1_GETS L2_AS>L2_AS [0x9b48040, line 0x9b48040]
1989406 0 0 Collector Miss_Get Col_NP>Col_P [0x9b48040, line 0x9b48040]
1989406 0 0 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
1989406 0 0 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
1989408 0 0 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
1989410 0 0 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
1989410 0 0 Collector Miss_Get Col_P>Col_P [0x9b48040, line 0x9b48040]
1989410 0 0 Collector Hit_Get Col_P>Col_F [0x9b48040, line 0x9b48040]
1989412 0 0 Collector Miss_Get Col_F>Col_F [0x9b48040, line 0x9b48040]
1989412 0 0 Collector Miss_Get_last Col_F>Col_NP [0x9b48040, line 0x9b48040]
1989420 0 7 L1CacheTransient_Local_GETS MM>I [0x9b48040, line 0x9b48040]
1989431 0 -1 Seq Done > [0x9b48048, line 0x9b48040] 53 cycles L1Cache_wCC No
1989431 0 0 L1Cache Data_All_Tokens IS>M_W [0x9b48040, line 0x9b48040] L1Cache-7
1989432 0 0 L1Cache Drop_Registration M_W>M_W [0x9b48040, line 0x9b48040]
1989432 0 -1 Seq Begin > [0x9b48040, line 0x9b48040]
1989436 0 -1 Seq Done > [0x9b48058, line 0x9b48040] 4 cycles L1Cache No
1989436 0 0 L1Cache Load M_W>M_W [0x9b48040, line 0x9b48040]
1989481 0 0 L1CacheUse_TimeoutNoStarvers M_W>M [0x9b48040, line 0x9b48040]
1990524 0 0 L1Cache L1_Replacement M>I [0x9b48040, line 0x9b48040]
1990531 0 1 L2CacheWriteback_All_Tokens L2_NP>L2_M [0x9b48040, line 0x9b48040]
1993000 7 -1 Seq Begin > [0x9b48040, line 0x9b48040]
BLOCK IN MORE THAN TWO BANKS: [0x9b48040, line 0x9b48040]
# Setup magic break hap
@def call_back_1(cpu):
pr("call back triggered\n")
@def hap_callback(user_arg, cpu, arg):
eax = cpu.eax
if eax == 1:
call_back_1(cpu)
else:
print "Unknown callback"
@SIM_hap_add_callback("Core_Magic_Instruction", hap_callback, None)
# Load checkpoint
read-configuration "~sbarrus/simics/home/MOESI_CMP_NUCA/radix.check"
# These commands instruct Simics to deliver all instruction
# fetches to Ruby/Opal, and disable the internal cache.
instruction-fetch-mode instruction-fetch-trace
istc-disable
dstc-disable
magic-break-enable
# Load modules
load-module ruby
# Setup
ruby0.setparam g_NUM_PROCESSORS 8
ruby0.setparam g_MEMORY_SIZE_BYTES 4294967296
ruby0.setparam g_PROCS_PER_CHIP 8
ruby0.setparam g_NUM_L2_BANKS 256
ruby0.setparam g_NUM_MEMORIES 8
ruby0.setparam g_NUM_DNUCA_BANK_SETS 16
ruby0.setparam L1_CACHE_ASSOC 2
ruby0.setparam L2_CACHE_ASSOC 16
ruby0.setparam_str g_NETWORK_TOPOLOGY FILE_SPECIFIED
ruby0.setparam_str g_DYNAMIC_TIMEOUT_ENABLED false
ruby0.setparam_str REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH true
ruby0.setparam_str g_CACHE_DESIGN NUCACOL
ruby0.setparam_str g_adaptive_routing false
ruby0.setparam NUMBER_OF_VIRTUAL_NETWORKS 7
ruby0.setparam g_endpoint_bandwidth 1000
ruby0.setparam_str g_NUCA_PREDICTOR_CONFIG DNUCA
ruby0.setparam_str ENABLE_MIGRATION true
ruby0.setparam_str COLLECTOR_HANDLES_OFF_CHIP_REQUESTS true
#ruby0.setparam_str PERFECT_DNUCA_SEARCH true
ruby0.setparam_str PERFECT_DNUCA_SEARCH false
# Initialization
ruby0.init
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