Re: [Gems-users] ruby0.dump-stats result is all 0

[Dan Gibson <degibson@xxxxxxxx>]

There are three things that could be going on here:
1) You haven't issued:
instruction-fetch-mode instruction fetch trace
dstc-disable
istc-disable
Failing to issue the above commands causes Simics to filter many memory
requests.
2) You are running simics in "fast" mode, which disables all timing
models. Be sure to use the -stall argument to simics on the command line.
3) The protocol you are simulating doesn't implement those statistics.
Some of the profiling functionality in Ruby is protocol-specific. That
is, some of our released protocols do not implement all statistics. It
is not very difficult to modify the protocols to add profiling -- there
are examples available in the various .sm files in the slicc/ directory.
Specifically, it looks like this particular protocol's L1 cache
statistics are not profiled.

Regards,
Dan Gibson

sample wrote:

>hi
>  I have made a CMP protocol successfully,and then simulator the debug_example,but when using ruby0.dump-status to check the misses result ,I find all is 0.
>  the rusult shows the instruction_executed: 137841895 [ 137841895 ],why Total_misses is 0.
>  I use GEMS1.1(after patch),simics 2.0.25,home/firststeps simulator
>  Can anybody show me out of the problem? thanks the friend and all that have helped me before.
>
>  the following is the part of the result:
>
>	
>
>Total_misses: 0
>total_misses: 0 [ 0 ]
>user_misses: 0 [ 0 ]
>supervisor_misses: 0 [ 0 ]
> 
>instruction_executed: 137841895 [ 137841895 ]
>cycles_per_instruction: 0.5 [ 0.5 ]
>misses_per_thousand_instructions: 0 [ 0 ]
> 
>transactions_started: 0 [ 0 ]
>transactions_ended: 0 [ 0 ]
>instructions_per_transaction: 0 [ 0 ]
>cycles_per_transaction: 0 [ 0 ]
>misses_per_transaction: 0 [ 0 ]
> 
>L1D_cache cache stats:
>  L1D_cache_total_misses: 0
>  L1D_cache_total_demand_misses: 0
>  L1D_cache_total_prefetches: 0
>  L1D_cache_total_sw_prefetches: 0
>  L1D_cache_total_hw_prefetches: 0
>  L1D_cache_misses_per_transaction: 0
>  L1D_cache_misses_per_instruction: 0
>  L1D_cache_instructions_per_misses: NaN
>
> 				
>
>　　　　　　　　sample
>　　　　　　　　yongyouziyoutoo@xxxxxxxx
>　　　　　　　　　　2006-06-15
>
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