[Gems-users] Re: Instruction Flow

[Luke Yen <lyen@xxxxxxxxxxx>]

  OK, I think I understand what you are trying to ask.  Given that we
attach latencies to loads and stores when executing with Opal and Ruby,
you might be wondering how this information is conveyed to Simics.

  When executing with Ruby and Simics, we have a stall/unstall interface
to Simics.  This means that we tell Simics to stall the processor until we
are finished simulating the memory request, some X cycles later.  Then we
send a message to Simics to unstall that processor, and this repeats until
we simulation terminates.

  However when executing with Opal and Simics, Opal itself is aware of the
latencies of loads and stores, but Simics is never informed.  When we
advance Simics the only information we convey to it is to step 1 (or more
cycles).  Thus it will appear to Simics that there are no
logical delays in the processors.

  What we have in mind as a fix to this problem is for Opal to convey
this latency information to Simics on an instrucion-level granularity,
which should affect the type of instruction flow you are referring to.

  Luke

On Thu, 8 Sep 2005, arrvindh shriraman wrote:

> If GEMS doesn't use MAI, I do not understand how OPAL
> regulates and changes instruction flow in SIMICS.
> For eg: Consider a multiprocessor system
>
> My jmp depends on a value to be loaded from the remote
> cache. Remote latency will influence number of
> instructions I speculate.
>
> Consider simple execution
>
> Load R1,<Mem>
> Load R2,<Mem>
> ....
> .....
> cmp R1,R2
> jnz
>
> How will this be handled in a CMP system or even a
> uniprocessor system when Load R1 (hits in cache) and
> Load R (misses), this will certainly influence
> instruction flow
>
> Arrvindh Shriraman
> Conputer Science Department
> University of Rochester
>