[Gems-users] model for main memory banks and controller

[Nauman Rafique <nrafique@xxxxxxxxxx>]

In the GEMS document submitted to CAN, it was mentioned that Ruby models memory
controllers and banks of main memory.
But in SLICC specifications, I found this for most protocols:
----------------------------------------------------------------------------
  action(d_sendData, "d", desc="Send data to requestor") {
    peek(requestQueue_in, RequestMsg) {
      enqueue(responseNetwork_out, ResponseMsg, latency="MEMORY_LATENCY") {
----------------------------------------------------------------------------

It looks like that would just delay the memory response by MEMORY_LATENCY.
Is the generated code taking care of banking (or memory controller)?

Thanks
-- 
Nauman