Re: [Gems-users] ruby caches

[Bradford Beckmann <beckmann@xxxxxxxxxxx>]

Chris,

You do not have to modify the code to set the L1 hit latency greater than
one when using the MSI_MOSI_CMP_directory protocol.  The previous
thread/msg you refer to is discussing a SMP protocol.  CMP protocols, like
MSI_MOSI_CMP_directory, are different because the L1 cache controller is
separate from the L2 cache controller.  Therefore, in these protocols, you
can have a multi-cycle L1D cache latency by setting
REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH = true, and then set the
SEQUENCER_TO_CONTROLLER_LATENCY equal to the L1 hit latency.  Multi-cycle
L1I cache latency is set by adding cycles to the opal fetch stages.

To my understanding, the instruction scheduler for opal automagically
allows load dependent instructions to issue as soon as the LD returns.
There is no simulation of squashing the issued dependents if the LD misses
in the L1D.  At least this is what Carl told me a couple years ago when I
asked a similar question.

> One more question about the cache size: g_DATA_BLOCK_BYTES is the size of a
> cache line, right?

Yes.  That is correct.

I hope that helps,

Brad